AX-SIGFOX
Ultra-Low Power,
AT Command Controlled,
Sigfox
)
Compliant
Transceiver IC for Up-Link
and Down-Link
OVERVIEW
Circuit Description
♦
♦
♦
♦
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AX−Sigfox is an ultra−low power single chip solution for
a node on the Sigfox network with both up− and down−link
functionality. The AX−Sigfox chip is delivered fully ready
for operation and contains all the necessary firmware to
transmit and receive data from the Sigfox network in
Europe. It connects to the customer product using a logic
level RS232 UART. AT commands are used to send frames
and configure radio parameters.
Features
2 GPIO pins with selectable sigma delta DAC
output functionality
2 GPIO pins with selectable output clock
3 GPIO pins selectable as SPI master interface
Integrated RX/TX switching with differential
antenna pins
Functionality and Ecosystem
•
Sigfox up−link and down−link functionality controlled
by AT commands
•
The AX−Sigfox IC is part of a whole development and
product ecosystem available from ON Semiconductor
for any Sigfox requirement. Other parts of the
ecosystem include
♦
Ready to go AX−Sigfox development kit with fully
functional AX−Sigfox module including Sigfox
subscription
♦
Sigfox Ready
®
certified reference design for the
AX−Sigfox IC
♦
MiniStamp by ON Semiconductor Sigfox modules
with SMA connector or chip antenna
♦
AX−Sigfox−API IC for customers wishing to write
their own application software based on the AXSEM
Sigfox Library
General Features
•
QFN40 5 mm x 7 mm package
•
Supply range 1.8 V
−
3.6 V
•
−40°C
to 85°C
•
Temperature sensor
•
Supply voltage measurements
•
10 GPIO pins
♦
4 GPIO pins with selectable voltage measure
functionality, differential (1 V or 10 V range) or
single ended (1 V range) with 10 bit resolution
Power Consumption
•
Ultra−low Power Consumption:
♦
Charge required to send a Sigfox OOB packet at
14 dBm output power: 0.28 C
♦
Deepsleep mode current: 100 nA
♦
Sleep mode current: 1.3
mA
♦
Standby mode current: 0.5 mA
♦
Continuous radio RX−mode at 869.525 MHz :
10 mA
♦
Continuous radio TX−mode at 868.130 MHz
19 mA @ 0 dBm
49 mA @ 14 dBm
High Performance Narrow−band Sigfox RF Transceiver
•
Receiver
♦
Carrier frequency 869.525 MHz
♦
Data−rate 600 bps FSK
♦
Sensitivity
−126
dBm @ 600 bps, 869.525 MHz, GFSK
♦
0 dBm maximum input power
•
Transmitter
♦
Carrier frequency 868.13 MHz
♦
Data−rate 100 bps PSK
♦
High efficiency, high linearity integrated power
amplifier
♦
Maximum output power 14 dBm
♦
Power level programmable in 1 dBm steps
Applications
Sigfox networks up−link and down−link.
©
Semiconductor Components Industries, LLC, 2016
March, 2016
−
Rev. 3
1
Publication Order Number:
AX−SIGFOX/D
AX−SIGFOX
BLOCK DIAGRAM
AX−Sigfox
CLKP
CLKN
TCXO
interface
RF synthesis
CAL
FILT
ANTP
ANTN
RX/TX
switch and
antenna
interface
Receive
Communication
controller
Transmit
UARTRX
UARTTX
UART
DAC
GPIO[9:0]
GPIO
ADC
CPU
RADIO_LED
CPU_LED
TX_LED
RX_LED
dedicated
status
outputs
power mode control
RAM
Program
memory
(FLASH)
Sigfox
application
VDD_ANA
VDD_IO
GND
VTCXO
Figure 1. Functional Block Diagram of the AX−SIGFOX
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2
RESET_N
AX−SIGFOX
Table 1. PIN FUNCTION DESCRIPTIONS
Symbol
VDD_ANA
GND
ANTP
ANTN
NC
GND
VDD_ANA
GND
FILT
L2
L1
NC
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
CPU_LED
RADIO_LED
VTCXO
GPIO9
UARTTX
UARTRX
RX_LED
TX_LED
NC
RESET_N
GND
VDD_IO
GPIO0
GPIO1
GPIO2
NC
NC
GPIO3
VDD_IO
CAL
NC
CLKN
Pin(s)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Type
P
P
A
A
N
P
P
P
A
A
A
N
I/O/PU
I/O/PU
I/O/PU
I/O/PU
I/O/PU
O
O
O
I/O/PU
O
I/PU
O
O
PD
I/PU
P
P
I/O/A/PU
I/O/A/PU
I/O/A/PU
N
N
I/O/A/PU
P
A
N
A
Description
Analog power output, decouple to neighboring GND
Ground, decouple to neighboring VDD_ANA
Differential antenna input/output
Differential antenna input/output
Do not connect
Ground, decouple to neighboring VDD_ANA
Analog power output, decouple to neighboring GND
Ground
Synthesizer filter
Must be connected to pin L1
Must be connected to pin L2
Do not connect
General purpose IO
General purpose IO, selectable SPI functionality (MISO)
General purpose IO, selectable SPI functionality (MOSI)
General purpose IO, selectable SPI functionality (SCK)
General purpose IO, selectable
SD
DAC functionality, selectable dock
functionality
CPU activity indicator
Radio activity indicator
TCXO power
General purpose IO, wakeup from deep sleep
UART transmit
UART receive
Receive activity indicator
Transmit activity indicator
Do not connect
Optional reset pin. Internal pull−up resistor is permanently enabled,
nevertheless it is recommended to connect this pin to VDD_IO if it is not used.
Ground
Unregulated power supply
General purpose IO, selectable ADC functionality, selectable
SD
DAC
functionality, selectable clock functionality
General purpose IO, selectable ADC functionality
General purpose IO, selectable ADC functionality
Do not connect
Do not connect
General purpose IO, selectable ADC functionality
Unregulated power supply
Connect to FILT as shown in the application diagram
Connect to Ground
TCXO interface
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AX−SIGFOX
Table 1. PIN FUNCTION DESCRIPTIONS
Symbol
CLKP
GND
Pin(s)
40
Center pad
Type
A
P
TCXO interface
Ground on center pad of QFN, must be connected
Description
A = analog input
I = digital input signal
O = digital output signal
PU = pull−up
I/O = digital input/output signal
N = not to be connected
P = power or ground
PD = pull−down
All digital inputs are Schmitt trigger inputs, digital input
and output levels are LVCMOS/LVTTL compatible. Pins
GPIO[3:0] must not be driven above VDD_IO, all other
digital inputs are 5 V tolerant. All GPIO pins and UARTRX
start up as input with pull−up. For explanations on how to
use the GPIO pins, see chapter “AT Commands”.
Table 2.
Pin
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
Possible GPIO Modes
0, 1, Z, U, A, T
0, 1, Z, U, A
0, 1, Z, U, A
0, 1, Z, U, A
0, 1, Z, U, T
0, 1, Z, U
0, 1, Z, U
0, 1, Z, U
0, 1, Z, U
0, 1, Z, U
0 = pin drives
1 = not to be connected
Z = pin is high impedance input
U = pin is input with pull−up
A = pin is analog input
T = pin is driven by clock or DAC
Pinout Drawing
VDD_IO
VDD_IO
29
GPIO3
GPIO2
GPIO1
31
40
39
38
37
36
35
34
33
32
VDD_ANA
GND
ANTP
ANTN
NC
GND
VDD_ANA
GND
GPIO0
30
CLKN
CLKP
CAL
NC
NC
NC
1
28
GND
RESET_N
NC
TXLED
RXLED
UARTRX
UARTTX
GPIO9
2
27
3
26
4
AX−Sigfox
QFN40
25
5
24
6
23
7
22
8
21
9
10
11
12
13
14
15
16
17
18
19
20
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
CPU_LED
Figure 2. Pinout Drawing (Top View)
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4
TX_LED
VTCXO
FILT
NC
L2
L1
AX−SIGFOX
SPECIFICATIONS
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol
VDD_IO
IDD
P
tot
P
i
I
I1
I
I2
I
O
V
ia
V
es
T
amb
T
stg
T
j
Supply voltage
Supply current
Total power consumption
Absolute maximum input power at receiver input
DC current into any pin except ANTP, ANTN
DC current into pins ANTP, ANTN
Output Current
Input voltage ANTP, ANTN pins
Input voltage digital pins
Electrostatic handling
Operating temperature
Storage temperature
Junction Temperature
HBM
−0.5
−0.5
−2000
−40
−65
ANTP and ANTN
pins in RX mode
−10
−100
Description
Condition
Min
−0.5
Max
5.5
200
800
10
10
100
40
5.5
5.5
2000
85
150
150
Units
V
mA
mW
dBm
mA
mA
mA
V
V
V
°C
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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Embedded System
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