PI7C9X7952
PCI Express® Dual UART
Datasheet
Revision 1.4
May 2013
3545 North 1ST Street, San Jose, CA 95134
Telephone: 1-877-PERICOM, (1-877-737-4266)
FAX: 408-435-1100
Internet: http://www.pericom.com
13-0092
PI7C9X7952
PCI Express® Dual UART
Datasheet
DISCLAIMER
The information contained in this document is proprietary and confidential to Pericom Semiconductor
Cooperation (PSC). No part of this document may be copied or reproduced in any form or by any means
without prior written consent of PSC.
The information in this document is subjected to change without notice. PSC retains the right to make
changes to this document at any time without notice. While the information contained in this document has
been checked for accuracy, such information is preliminary, and PSC does not warrant the accuracy and
completeness of such information. PSC does not assume any liability or responsibility for damages arising
from any use of the information contained in this document.
LIFE SUPPORT POLICY
Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life
support devices or systems unless a specific written agreement pertaining to such intended use is executed
between the manufacturer and an officer of PSC.
1)
Life support devices or system are devices or systems which:
a)
Are intended for surgical implant into the body or
b)
Support or sustain life and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to
the user.
2)
A critical component is any component of a life support device or system whose failure to perform
can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or
specifications at any time, without notice, in order to improve design or performance and to supply the best
possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry
described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes
no representations that circuitry described herein is free from patent infringement or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent,
patent rights or other rights, of Pericom Semiconductor Corporation.
All other trademarks are of their respective companies.
Page 2 of 68
May 2013 – Revision 1.4
Pericom Semiconductor
13-0092
PI7C9X7952
PCI Express® Dual UART
Datasheet
REVISION HISTORY
Date
10/31/07
Revision Number
0.1
Description
Preliminary Datasheet
Fixed the diagrams
Corrected Chapter 4.2 Pin Description (RREF, GPIO[7])
Updated Chapter 6 PCI Express Registers(6.2.42 [3], 6.2.36 UART Driver
Setting, 6.2.41 GPIO Control Register )
Revised Chapter 7.1 Registers in I/O Mode
Updated Chapter 11 Ordering Info
Updated Chapter 4 Pin Assignment (description for shared pins added,
MODE_SEL changed to DRIVER_SEL, VAUX changed to VDDCAUX)
Updated Chapter 6 PCI Express Register Description (B4h, D0h)
Updated Chapter 7 UART Register Description
Updated Chapter 8 EEPROM Interface
Updated 1 Features (Clock prescaler, Data frame size, Power Dissipation)
Corrected 3 General Description
Updated 4 Pin Assignment (description for shared pins added, MODE_SEL
changed to DRIVER_SEL, VAUX changed to VDDCAUX, WAKEUP_L,
CLKINP, CLKINN)
Added 5.2.4 Mode Selection, 5.2.5 450/550 Mode, 5.2.6 Enhanced 550 Mode,
5.2.7 Enhanced 950 Mode
Corrected 5.2.8 Transmit and Receive FIFOs, 5.2.9 Automated Flow Control
Modified 5.2.12 Baud Rate Generation
Updated 6 PCI Express Register Description (6.2.36, 6.2.42)
Updated Format (6.2.20, 6.2.36, 6.2.54, 6.2.55, 6.2.57)
Updated Chapter 7 UART Register Description (7.1.6 LCR Bit[5:0], 7.1.7 MCR
Bit[5] and Bit[7], 7.1.9 MSR Bit[3:0], 7.2.6 LCR Bit[5:0], 7.2.7 MCR Bit[5] and
Bit[7], 7.2.9 MSR Bit[3:0], 7.2.11 DLL, 7.2.12 DLH, 7.2.13 EFR, 7.2.18 ACR
Bit[7:2], 7.2.23 CPRM)
Updated Chapter 8.3 EEPROM Space Address Map And Description (00h, 0Ah,
40h)
Added Chapter 9 Electrical Specification
Corrected 9.2 DC Specification
Updated 9.3 AC Specification
Added 10 Clock Scheme
Updated Chapter 1 Features (added Industrial Temperature Range)
Updated 9.1 Absolute Maximum Ratings: Ambient Temperature with power
applied
Updated 7.1.13 Sample Clock Register and 7.2.27 Sample Clock Register
Updated Chapter 12 Ordering Information
Removed “Preliminary” and “Confidential” references
Corrected Figure 3-1 PI7C9X7952 Block Diagram (SYN_UART_CLK removed)
Corrected Section 4.2.1 UART Interface (SYNCLK_IN_EN and
SYN_UART_CLK removed)
Corrected Figure 5-2 Internal Loopback in PI7C7952
Corrected Figure 5-3 Crystal Oscillator as the Clock Source (14.7456 MHz)
Corrected Section 7.1.7 Modem Control Register (Bit[5]), 7.1.10 Special
Function Register (Bit[4]), 7.2.7 Modem Control Register (Bit[5]), 7.2.10
Special Function Register (Bit[4]), 7.2.29 Receive FIFO Data Registers, 7.2.30
Transmit FIFO Data Register, 7.2.31
Added internal pull-up and pull-down information to UART Interface, System
Interface, Test Signal, and EEPROM pins in Section 4.
Updated Figure 5-3 Crystal Oscillator as the Clock Source
Updated Section 6.2.24 Message Signaled Interrupt (MSI) Next Item Pointer 8Ch
Added Section 6.2.25 Message Address Register – Offset 90h
Added Section 6.2.26 Message Upper Address Register – Offset 94h
Added Section 6.2.27 Message Data Register – Offset 98h
Updated Section 4.1 Pin List (SR_DO and SR_DI)
Updated Section 4.2.5 EEPROM Interface (SR_DO and SR_DI)
12/28/07
0.2
4/22/08
0.3
8/13/08
11/25/08
3/6/09
0.4
1.0
1.1
4/21/09
9/24/09
1.2
1.3
5/15/13
1.4
Page 3 of 68
May 2013 – Revision 1.4
Pericom Semiconductor
13-0092
PI7C9X7952
PCI Express® Dual UART
Datasheet
Table of Contents
1.
2.
3.
4.
FEATURES ............................................................................................................................................9
APPLICATIONS ...................................................................................................................................9
GENERAL DESCRIPTION ...............................................................................................................10
PIN ASSIGNMENT ............................................................................................................................. 11
4.1. PIN LIST
OF
128-PIN LQFP .......................................................................................................... 11
4.2. PIN DESCRIPTION ......................................................................................................................12
4.2.1.
UART INTERFACE ................................................................................................................12
4.2.2.
PCI EXPRESS INTERFACE ..................................................................................................13
4.2.3.
SYSTEM INTERFACE............................................................................................................13
4.2.4.
TEST SIGNALS ......................................................................................................................14
4.2.5.
EEPROM INTERFACE ..........................................................................................................15
4.2.6.
POWER PINS ........................................................................................................................15
5.
FUNCTIONAL DESCRIPTION ........................................................................................................16
5.1. CONFIGURATION SPACE ..........................................................................................................16
5.1.1.
PCI Express Configuration Space .........................................................................................16
5.1.2.
UART Configuration Space ...................................................................................................16
5.2. DEVICE OPERATION..................................................................................................................17
5.2.1.
Configuration Access .............................................................................................................17
5.2.2.
I/O Reads/Writes ....................................................................................................................17
5.2.3.
Memory Reads/Writes ............................................................................................................17
5.2.4.
Mode Selection ......................................................................................................................18
5.2.5.
450/550 Mode ........................................................................................................................18
5.2.6.
Enhanced 550 Mode ..............................................................................................................18
5.2.7.
Enhanced 950 Mode ..............................................................................................................18
5.2.8.
Transmit and Receive FIFOs .................................................................................................18
5.2.9.
Automated Flow Control........................................................................................................20
5.2.10. Internal Loopback..................................................................................................................21
5.2.11. Crystal Oscillator ..................................................................................................................22
5.2.12. Baud Rate Generation ...........................................................................................................23
5.2.13. Power Management ...............................................................................................................23
6.
PCI EXPRESS REGISTER DESCRIPTION ...................................................................................24
6.1. REGISTER TYPES .......................................................................................................................24
6.2. CONFIGURATION REGISTERS .................................................................................................24
6.2.1.
VENDOR ID REGISTER – OFFSET 00h ..............................................................................25
6.2.2.
DEVICE ID REGISTER – OFFSET 00h................................................................................25
6.2.3.
COMMAND REGISTER – OFFSET 04h ...............................................................................25
6.2.4.
STATUS REGISTER – OFFSET 04h......................................................................................25
6.2.5.
REVISION ID REGISTER – OFFSET 08h ............................................................................26
6.2.6.
CLASS CODE REGISTER – OFFSET 08h ............................................................................26
6.2.7.
CACHE LINE REGISTER – OFFSET 0Ch............................................................................26
6.2.8.
MASTER LATENCY TIMER REGISTER – OFFSET 0Ch .....................................................26
6.2.9.
HEADER TYPE REGISTER – OFFSET 0Ch.........................................................................27
6.2.10. BASE ADDRESS REGISTER 0 – OFFSET 10h .....................................................................27
6.2.11. BASE ADDRESS REGISTER 1 – OFFSET 14h .....................................................................27
6.2.12. SUBSYSTEM VENDOR REGISTER – OFFSET 2Ch ............................................................27
6.2.13. SUBSYSTEM ID REGISTER – OFFSET 2Ch........................................................................27
Page 4 of 68
May 2013 – Revision 1.4
Pericom Semiconductor
13-0092
PI7C9X7952
PCI Express® Dual UART
Datasheet
6.2.14.
6.2.15.
6.2.16.
6.2.17.
6.2.18.
6.2.19.
6.2.20.
6.2.21.
6.2.22.
6.2.23.
6.2.24.
6.2.25.
6.2.26.
6.2.27.
6.2.28.
6.2.29.
6.2.30.
6.2.31.
6.2.32.
6.2.33.
6.2.34.
6.2.35.
6.2.36.
6.2.37.
6.2.38.
6.2.39.
6.2.40.
6.2.41.
6.2.42.
6.2.43.
6.2.44.
6.2.45.
6.2.46.
6.2.47.
6.2.48.
6.2.49.
6.2.50.
6.2.51.
6.2.52.
6.2.53.
6.2.54.
6.2.55.
6.2.56.
100h
6.2.57.
6.2.58.
6.2.59.
6.2.60.
6.2.61.
6.2.62.
6.2.63.
6.2.64.
6.2.65.
CAPABILITIES POINTER REGISTER – OFFSET 34h .........................................................27
INTERRUPT LINE REGISTER – OFFSET 3Ch ....................................................................27
INTERRUPT PIN REGISTER – OFFSET 3Ch ......................................................................28
POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h ...............................28
NEXT ITEM POINTER REGISTER – OFFSET 80h..............................................................28
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h ................................28
POWER MANAGEMENT DATA REGISTER – OFFSET 84h ...............................................28
PPB SUPPORT EXTENSIONS – OFFSET 84h.....................................................................29
PM DATA REGISTER – OFFSET 84h ...................................................................................29
MESSAGE SIGNALED INTERRUPTS (MSI) Capability ID Register 8Ch ...........................29
MESSAGE SIGNALED INTERRUPTS (MSI) NEXT ITEM POINTER 8Ch ..........................29
MESSAGE ADDRESS REGISTER – OFFSET 90h................................................................29
MESSAGE UPPER ADDRESS REGISTER – OFFSET 94h ..................................................29
MESSAGE DATA REGISTER – OFFSET 98h .......................................................................30
VPD CAPABILITY ID REGISTER – OFFSET 9Ch ...............................................................30
NEXT ITEM POINTER REGISTER – OFFSET 9Ch .............................................................30
VPD REGISTER – OFFSET 9Ch ..........................................................................................30
VPD DATA REGISTER – OFFSET A0h ................................................................................30
VENDOR SPECIFIC CAPABILITY ID REGISTER – OFFSET A4h .....................................30
NEXT ITEM POINTER REGISTER – OFFSET A4h .............................................................31
LENGTH REGISTER – OFFSET A4h ...................................................................................31
XPIP CSR0 – OFFSET A8h (Test Purpose Only) ..................................................................31
XPIP CSR1 – OFFSET ACh (Test Purpose Only) .................................................................31
REPLAY TIME-OUT COUNTER – OFFSET B0h .................................................................31
ACKNOWLEDGE LATENCY TIMER – OFFSET B0h ..........................................................31
UART DRIVE SETTING – OFFSET B4h ..............................................................................31
Power Management Control Parameter – OFFSET B8h ......................................................32
DEBUG REGISTER 1 – OFFSET BCh (Test Purpose Only) ................................................32
DEBUG REGISTER 2 – OFFSET C0h (Test Purpose Only) .................................................32
DEBUG REGISTER 3 – OFFSET C4h (Test Purpose Only) .................................................32
DEBUG REGISTER 4 – OFFSET C8h (Test Purpose Only) .................................................32
GPIO CONTROL REGISTER – OFFSET D8h ......................................................................33
EEPROM CONTROL REGISTER – OFFSET DCh...............................................................33
PCI EXPRESS CAPABILITY ID REGISTER – OFFSET E0h ................................................33
NEXT ITEM POINTER REGISTER – OFFSET E0h .............................................................33
PCI EXPRESS CAPABILITIES REGISTER – OFFSET E0h .................................................34
DEVICE CAPABILITIES REGISTER – OFFSET E4h ...........................................................34
DEVICE CONTROL REGISTER – OFFSET E8h .................................................................34
DEVICE STATUS REGISTER – OFFSET E8h ......................................................................35
LINK CAPABILITIES REGISTER – OFFSET ECh ...............................................................36
LINK CONTROL REGISTER – OFFSET F0h .......................................................................36
LINK STATUS REGISTER – OFFSET F0h ...........................................................................37
PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY ID REGISTER – OFFSET
37
CAPABILITY VERSION – OFFSET 100h ..............................................................................37
NEXT ITEM POINTER REGISTER – OFFSET 100h ............................................................37
UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h .....................................37
UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h........................................38
UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch ................................39
CORRECTABLE ERROR STATUS REGISTER – OFFSET 110h...........................................40
CORRECTABLE ERROR MASK REGISTER – OFFSET 114h .............................................40
ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h .............41
HEADER LOG REGISTER – OFFSET From 11Ch to 128h .................................................41
Page 5 of 68
May 2013 – Revision 1.4
Pericom Semiconductor
13-0092
京公网安备 11010802033920号
EEWORLD
