PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™
with Equalization & Emphasis
Features
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Up to 5.0Gbps PCIe® 2.0 Serial ReDriver™
Supporting 8 differential channels or 4 lanes of PCIe Interface
Pin strapped and I
2
C configuration controls
Adjustable receiver equalization
Adjustable transmitter amplitude and de-emphasis
Variable input an output termination
1:2 channel broadcast
Channel loop-back
Electrical Idle fully supported
Receiver detect and individual output control
Single supply voltage, 1.2V ± 0.05V
Power down modes
Packaging: 100-contact LBGA, Pb-free & Green
Description
Pericom Semiconductor’s PI2EQX5804C is a low power, PCIe®
compliant signal ReDriver™. The device provides programmable
equalization, amplification, and de-emphasis by using 8 select
bits, to optimize performance over a variety of physical mediums
by reducing Inter-symbol interference.
PI2EQX5804C supports eight 100-Ohm Differential CML
data I/O’s between the Protocol ASIC to a switch fabric, across
a backplane, or extends the signals across other distant data
pathways on the user’s platform.
The integrated equalization circuitry provides
fl
exibility with
signal integrity of the PCIe signal before the ReDriver, whereas
the integrated de-emphasis circuitry provides
fl
exibility with
signal integrity of the signal after the ReDriver.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX5804C also provides power management Stand-by mode
operated by a Power Down pin.
Block Diagram
+
−
xyRx+
xyRx-
+
−
+
Equalizer
−
xyTx+
xyTx-
Input level detect
to control logic
Output
Controls
Pin Configuration (Top-Side View)
1
2
3
4
5
6
7
8
9
10
A
VDD
B0TX-
B0TX+
VDD
SCL
SDA
VDD
B0RX+
B0RX-
VDD
B
A1RX+
GND
GND
A0RX -
DE_A
VDD
A0TX-
GND
GND
A1TX+
xyTx+
xyTx-
+
−
Output
Controls
A
B
Input level detect
to control logic
Equalizer
+
−
+
−
C
A1RX-
xyRx+
xyRx-
GND
GND
A0RX+
NC
PD#
A0TX+
GND
GND
A1TX -
D
VDD
B1TX+ B1TX-
VDD
D2_A
NC
VDD
B1RX - B1RX+ VDD
Data Lane Repeats 4 Times
SELy_x
Sy_x
Dy_x
DE_x
PD#
SDA
SCL
Mode
E
SEL0_A SEL1_A SEL2_A D0_A
D1_A
S0_A
RXD_A S1_A
SIG_A RX50_A
Control registers
& logic
Power
Management
I
2
C Control
LB#
RXD_x
RES_x
F
RX50_B SIG_B
S1_B
RXD_B S0_B
A1
SEL2_B
LB#
SEL1_B SEL0_B
G
VDD
A2RX-
A2RX+
VDD
MODE D0_B
VDD
A2TX+
A2TX -
VDD
H
Ax
B2TX+
GND
GND
B3TX-
DE_B
A0
B3RX -
GND
GND
B2RX+
J
B2TX-
GND
GND
B3TX+ RESET# D1_B
B3RX+
GND
GND B2RX-
K
VDD
A3RX+ A3RX-
VDD
D2_B
A4
VDD
A3TX-
A3TX+
VDD
09-0001
1
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Pin #
Data Signals
C4
B4
C7
B7
B1
C1
B10
C10
G3
G2
G8
G9
K2
K3
K9
K8
A8
A9
A3
A2
D9
D8
D2
D3
H10
J10
H1
J1
J7
H7
J4
H4
Control Signals
H6, F6, K6
E4, E5, D5
G6, J6, K5
B5
Pin Name
A0RX+,
A0RX-
A0TX+,
A0TX-
A1RX+,
A1RX-
A1TX+,
A1TX-
A2RX+,
A2RX-
A2TX+,
A2TX-
A3RX+,
A3RX-
A3TX+,
A3TX-
B0RX+,
B0RX-
B0TX+,
B0TX-
B1RX+,
B1RX-
B1TX+,
B1TX-
B2RX+,
B2RX-
B2TX+,
B2TX-
B3RX+,
B3RX-
B3TX+,
B3TX-
A0, A1, A4
D[0:2]_A
D[0:2]_B
DE_A
Type
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
I
I
Description
CML inputs for Channel A0, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel A0, with internal 50-Ohm pull up during normal opera-
tion and 2K-Ohm pull up otherwise.
CML inputs for Channel A1, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel A1, with internal 50-Ohm pull up during normal opera-
tion and 2K-Ohm pull up otherwise.
CML inputs for Channel A2, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel A2, with internal 50-Ohm pull up during normal opera-
tion and 2K-Ohm pull up otherwise.
CML inputs for Channel A3 with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel A3, with internal 50-Ohm pull up during normal opera-
tion and 2K-Ohm pull up otherwise.
CML inputs for Channel B0, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel B0, with internal 50-Ohm pull up during normal opera-
tion and 2K-Ohm pull up otherwise.
CML inputs for Channel B1, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel B1, with internal 50-Ohm pull up during normal opera-
tion and 2K-Ohm pull up otherwise.
CML inputs for Channel B2, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel B2, with internal 50-Ohm pull up during normal opera-
tion and 2K-Ohm pull up otherwise.
CML inputs for Channel B3, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel B3, with internal 50-Ohm pull up during normal opera-
tion and 2K-Ohm pull up otherwise.
I
2
C programmable address bit A0, A1 and A4.
Selection pins for Channel Ax emphasis (See emphasis Configuration Table) w/
100K-Ohm internal pull up
Selection pins for Channel Bx emphasis (See emphasis Configuration Table) w/
100K-Ohm internal pull up
De-emphasis enable input for Channel A0, A1, A2 and A3 with internal 100K-
Ohm pull-up resistor. Set high selects output de-emphasis and set low selects
output pre-emphasis.
09-0001
2
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Pin #
H5
F8
Pin Name
DE_B
LB#
Type
I
I
G5
MODE
I
C6
D6
C5
J5
PD#
NC
NC
RESET#
I
I
E10
F1
E7
F4
E6, E8
F5, F3
A5
A6
E1, E2, E3
RX50_A
RX50_B
RXD_A
RXD_B
S[0:1]_A
S[0:1]_B
SCL
SDA
SEL[0:2]_A
O
O
I
I
I
I
I/O
I/O
I
Description
De-emphasis enable input for Channel B0, B1, B2 and B3 with internal 100K-
Ohm pull-up resistor. Set high selects output de-emphasis and set low selects
output pre-emphasis.
Input with internal 100K-Ohm pull-up resistor. LB# = High or open for normal
operation. LB# = Low for loopback connection of A_RX to A_TX and B_TX.
Input switch between pin control and I
2
C control with internal 100k-ohm pull-up
resistor. A LVCMOS high level selects input pin control, and disables I
2
C opera-
tion. Note, during startup, input status of the control pin (LB#, RESET#, PD#,
RXD_A/B, SEL0-2_A/B, D0-2_A/B, S0-1_A/B, DE_A/B) will be latched to the
initial state of some I
2
C control pins only once.
Input with internal 100K-Ohm pull-up resistor, PD# =High or open is normal
operation, PD# =Low disable the IC, and set IC to power down mode, both input
and output go Hi-Z.
No Connect
No Connect
RESET# is an active low channel reset input for Channel A0, B0, A1, B1, A2,
B2, A3 and B3 with internal 100K-Ohm pull-up resistor. When low, the receiver
detection cycle is reset, and normal detection cycle is started after the pin goes
high.
Receiver detect output pin for Channel A0. RX50_A=High
indicates that a 50-Ohm termination was sensed at the A0TX+/- outputs.
Receiver detect output pin for Channel B0. RX50_B=High
indicates that a 50-Ohm termination was sensed at the B0TX+/- outputs.
Receiver detect enable input for Channel A0, A1, A2 and A3 with internal 100K-
Ohm pull-up resistor.
Receiver detect enable input for Channel B0, B1, B2 and B3 with internal 100K-
Ohm pull-up resistor.
Selection pins for Channel Ax output level (see Output Swing Configuration
Table) w/ 100K-Ohm internal pull up
Selection pins for Channel Bx output level (see Output Swing Configuration
Table) w/ 100K-Ohm internal pull up
I
2
C SCL clock input.
I
2
C SDA data input.
Selection pins for Channel Ax equalization (see Equalizer Configuration Table)
w/ 100K-Ohm internal pull up
09-0001
3
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Pin #
F10, F9, F7
E9
F2
Power Pins
Pin Name
SEL[0:2]_B
SIG_A
SIG_B
Type
I
O
O
Description
Selection pins for Channel Bx Equalization (see Equalizer Configuration Table)
w/ 100K-Ohm internal pull up
Signal detect output pin for Channel A0. SIG_A=High represents a input signal >
threshold at the differential inputs.
Signal detect output pin for Channel B0. SIG_B=High represents a input signal >
threshold at the differential inputs.
B2, B3, B8, B9, C2,
C3, C8, C9, H2,
GND
H3, H8, H9, J2, J3,
J8, J9
PWR
Supply Ground
A1, A4, A7, A10,
B6, D1, D4, D7,
D10, G1, G4, G7,
G10, K1, K4, K7,
K10
V
DD
PWR
1.2V Supply Voltage
DESCRIPTION of OPERATION
Configuration Modes
Device configuration can be performed in two ways depending on the state of the MODE input. MODE de-
termines whether IC configuration status is from the input pins or via I
2
C control. When MODE is set high,
the configuration input pins set the configuration operating state as stored in configuration registers. While
MODE is set high, changes to these control registers are disabled and the initial condition is protected from
any changes to insuring a known operating state. When the MODE pin is low, reprogramming of these control
registers via I
2
C is allowed. Note that the MODE pin is not latched, and is always active to enable or disable
I
2
C access.
During initial power-on, the value at the configuration input pins: LB#, RESET#, PD#, RXD_A and RXD_B,
DE_A, DE_B, SEL0_A, SEL1_A, SEL2_A, D0_A, D1_A, D2_A, S0_A, S1_A, SEL0_B, SEL1_B, SEL2_B,
D0_B, D1_B, D2_B, S0_B, S1_B, will be latched to the configuration registers as initial startup states.
09-0001
4
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
Equalization & Emphasis
Equalizer Configuration
The PI2EQX5804C input equalizer compensates for signal attenuation and Inter-Symbol Interference (ISI) re-
sulting from long signal traces or cables, vias, signal crosstalk and other factors, by boosting the gain of high-
frequency signal components. Because either too little, or too much, signal compensation may be non-optimal
eight levels are provided to adjust for any application.
Equalizer configuration is performed in two ways determined by the state of the MODE pin. When the device
fi
rst powers up, the SELx_[A:B] input pins are read into the appropriate control registers to set the equalization
characteristic. If the MODE pin is low, reprogramming of these control registers via I
2
C is allowed.
Each group of four channels, A and B, has separate equalization control, and all four channels within the group
are assigned the same configuration state. The Equalizer Selection table below describes pin strapping options
and associated operation of the equalizer. Refer to the section on I
2
C programming for information on soft-
ware configuration of the equalizer.
Equalizer Selection
SEL2_[A:B]
0
0
0
0
1
1
1
1
SEL1_[A:B]
0
0
1
1
0
0
1
1
SEL0_[A:B]
0
1
0
1
0
1
0
1
@1.25GHz
0.5dB
0.6dB
1.0dB
1.9dB
2.8dB
3.6dB
5.0dB
7.7dB
@2.5GHz
1.2dB
1.5dB
2.6dB
4.3dB
5.8dB
7.1dB
9.0dB
12.3dB
Output Configuration
The PI2EQX5804C provides
fl
exible output strength and emphasis controls to provide the optimum signal to
pre-compensate for losses across long trace or noisy environments so that the receiver gets a clean eye open-
ing. Control of output configuration is grouped for the A and B channels, so that each channel within the
group has the same setting.
Output configuration is performed in two ways depending on the state of the MODE pin. When the device
fi
rst powers up, the Sx_[A:B], and Dx_[A:B] input pins are read into the appropriate control registers to set the
power-on state. If the MODE pin is low, reprogramming of these control registers via I
2
C is allowed.
The Output Swing Control table shows available configuration settings for output level control, as specified
using the Sx_y pins and registers.
09-0001
5
PS8926B
06/08/09
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