CD4724BC 8-Bit Addressable Latch
October 1987
Revised January 1999
CD4724BC
8-Bit Addressable Latch
General Description
The CD4724BC is an 8-bit addressable latch with three
address inputs (A0–A2), an active low enable input (E),
active high clear input (CL), a data input (D) and eight out-
puts (Q0–Q7).
Data is entered into a particular bit in the latch when that is
addressed by the address inputs and the enable (E) is
LOW. Data entry is inhibited when enable (E) is HIGH.
When clear (CL) and enable (E) are HIGH, all outputs are
LOW. When clear (CL) is HIGH and enable (E) is LOW, the
channel demultiplexing occurs. The bit that is addressed
has an active output which follows the data input while all
unaddressed bits are held LOW. When operating in the
addressable latch mode (E
=
CL
=
LOW), changing more
than one bit of the address could impose a transient wrong
address. Therefore, this should only be done while in the
memory mode (E
=
HIGH, CL
=
LOW).
Features
s
Wide supply voltage range:
s
High noise immunity:
s
Low power TTL compatibility:
fan out of 2 driving 74L or 1 driving 74LS
s
Serial to parallel capability
s
Storage register capability
s
Random (addressable) data entry
s
Active high demultiplexing capability
s
Common active high clear
3.0V to 15V
0.45 V
DD
(typ.)
Ordering Code:
Order Number
CD4724BCM
CD4724BCN
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Truth Table
Mode Selection
E
CL
Addressed
Latch
L
H
L
H
L
L
Follows Data
Unaddressed
Latch
Holds Previous
Data
Addressable
Latch
Memory
Demultiplexer
Clear
Mode
Hold Previous Holds Previous
Data
Data
Reset to “0”
Reset to “0”
H Follows Data
H Reset to “0”
Top View
© 1999 Fairchild Semiconductor Corporation
DS006003.prf
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CD4724BC
Absolute Maximum Ratings
(Note 1)
(Note 2)
DC Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Storage Temperature (T
S
)
Power Dissipation (P
D
)
Dual-In-Line
Small Outline
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260°C
(Note 2)
700 mW
500 mW
−0.5V
to
+18
V
DC
−0.5V
to V
DD
+0.5
V
DC
−65°C
to
+150°C
Recommended Operating
Conditions
(Note 2)
DC Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Operating Temperature Range (T
A
)
3.0V to 15 V
DC
0V to V
DD
V
DC
−40°C
to
+85°C
Note 1:
“Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed; they are not meant to imply that
the devices should be operated at these limits. The tables of “Recom-
mended Operating Conditions” and Electrical Characteristics” provide con-
ditions for actual device operation.
Note 2:
V
SS
=
0V unless otherwise specified.
DC Electrical Characteristics
Symbol
I
DD
Parameter
Quiescent Device
Current
V
OL
LOW Level
Output Voltage
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
|I
O
|
≤
1
µA
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
OH
HIGH Level
Output Voltage
|I
O
|
≤
1
µA
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
IL
LOW Level
Input Voltage
V
IH
HIGH Level
Input Voltage
I
OL
LOW Level Output
Current
(Note 3)
I
OH
HIGH Level Output
Current
(Note 3)
I
IN
Input Current
Conditions
−40°C
Min
Max
20
40
80
0.05
0.05
0.05
4.95
9.95
14.95
1.5
3.0
4.0
3.5
7.0
11.0
0.52
1.3
3.6
−0.52
−1.3
−3.6
−0.30
0.30
3.5
7.0
11.0
0.44
1.1
3.0
−0.44
−1.1
−3.0
4.95
9.95
14.95
Min
+25°C
Typ
0.02
0.02
0.02
0
0
0
5.0
10
15
2.25
4.5
6.75
2.75
5.5
8.25
0.88
2.25
8.8
−0.88
−2.25
−8.8
−10
−5
10
−5
−0.30
0.30
1.5
3.0
4.0
Max
20
40
80
0.05
0.05
0.05
+85°C
Min
Max
150
300
600
0.05
0.05
0.05
4.95
9.95
14.95
1.5
3.0
4.0
3.5
7.0
11.0
0.36
0.9
2.4
−0.36
−0.9
−2.4
−1.0
1.0
Units
µA
µA
µA
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
µA
µA
V
DD
=
5V, V
O
=
0.5V or 4.5V
V
DD
=
10V, V
O
=
1V or 9V
V
DD
=
15V, V
O
=
1.5V or 13.5V
V
DD
=
5V, V
O
=
0.5V or 4.5V
V
DD
=
10V, V
O
=
1V or 9V
V
DD
=
15V, V
O
=
1.5V or 13.5V
V
DD
=
5V, V
O
=
0.4V
V
DD
=
10V, V
O
=
0.5V
V
DD
=
15V, V
O
=
1.5V
V
DD
=
5V, V
O
=
4.6V
V
DD
=
10V, V
O
=
9.5V
V
DD
=
15V, V
O
=
13.5V
V
DD
=
15V, V
IN
=
0V
V
DD
=
15V, V
IN
=
15V
Note 3:
I
OL
and I
OH
are tested one output at a time.
3
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CD4724BC
AC Electrical Characteristics
Symbol
t
PHL, tPLH
Parameter
Propagation Delay
Data to Output
t
PLH
, t
PHL
Propagation Delay
Enable to Output
t
PHL
Propagation Delay
Clear to Output
t
PLH
, t
PHL
Propagation Delay
Address to Output
t
THL
, t
TLH
Transition Time
(Any Output)
T
WH
, T
WL
Minimum Data
Pulse Width
t
WH
, t
WL
Minimum Address
Pulse Width
t
WH
Minimum Clear
Pulse Width
t
SU
Minimum Setup Time
Data to E
t
H
Minimum Hold Time
Data to E
t
SU
Minimum Setup Time
Address to E
t
H
Minimum Hold Time
Address to E
C
PD
C
IN
Power Dissipation
Capacitance
Input Capacitance
(Note 4)
Conditions
Min
Typ
200
75
50
200
80
60
175
80
65
225
100
75
100
50
40
100
50
40
200
100
65
75
40
25
40
20
15
60
30
25
−15
0
0
−50
−20
−15
100
5.0
7.5
Max
400
150
100
400
160
120
350
160
130
450
200
150
200
100
80
200
100
80
400
200
125
150
75
50
80
40
30
120
60
50
50
30
20
15
10
5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
T
A
=
25
°
C, C
L
=
50 pF, R
L
=
200k, Input t
r
=
t
f
=
20 ns, unless otherwise noted
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
Per Package
(Note 5)
Any Input
Note 4:
AC Parameters are guaranteed by DC correlated testing.
Note 5:
Dynamic power dissipation (P
D
) is given by: P
D
=
(C
PD
+
C
L
) V
CC2
f
+
P
Q
; where C
L
=
load capacitance; f
=
frequency of operation; for further details,
see Application Note AN-90, “Family Characteristics”.
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