DRC-10520
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®
HIGH POWER 16-BIT DIGITAL-TO-
RESOLVER (D/R) CONVERTERS
FEATURES
•
2 VA Drive Capacity
•
8-Bit/2-Byte Double Buffered
Transparent Latch
•
Resolution: 16 Bits
Accuracy: to 1 Minute
•
Power Amplifier Uses AC Reference
or DC Supplies
•
BIT
Output
DESCRIPTION
The DRC-10520 is a 16 bit, 32 pin triple DIP Digital-to-Resolver converter
with 2 VA drive capability. It features a power amplifier that may be driven by
a standard ±15 VDC power supply or by the reference source (when used
with the optional power transformer DDC/PN 29306). The DRC-10520 pro-
vides compatibility with microprocessors through its 8-bit 2-byte transparent
input latch. Data input is natural binary angles in TTL compatible parallel
positive logic format.
The DRC-10520 is comprised of a high accuracy Digital-to-Resolver con-
verter and a dual power amplifier stage that has high accuracy and low scale
factor variation. In addition, a standard BIT circuit provides a digital overcur-
rent signal output. A logic “0” BIT output indicates an overcurrent condition in
the sine or cosine outputs. Reference inputs are scalable with external resis-
tors. Loss of the reference signal will not damage the converter.
APPLICATION
The DRC-10520 can be used where digitized shaft angle data must be con-
verted to an analog format for driving control transformers. With its built-in
input latches, the DRC-10520 is especially compatible with a microprocessor-
based system including flight simulators, flight instrumentation, fire control
systems, radar and navigation systems, and air data computers.
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
All trademarks are the property of their respective owners.
©
1985, 1999 Data Device Corporation
Data Device Corporation
www.ddc-web.com
+15 V DC
DRC-10520
S
SIN
OPTIONAL
SCOTT-T
TRANSFORMER
DUAL
HI POWER
AMPLIFIERS
COS
BIT
BIT 1-16
TRANSPARENT
LATCH
TRANSPARENT
LATCH
LOGIC "0" INDICATES
OVER CURRENT
-15 V DC
+V
OR
+15
-V
OR
-15
SYNCHRO
OUTPUT
D/R
CONVERTER
HIGH ACCURACY
LOW SCALE FACTOR
VARIATION
C
LM
LA
BITS 1-8 BITS 9-16
LL
RH
RL
2
FIGURE 1. DRC-10520 BLOCK DIAGRAM
DRC-10520
T-7/08-0
tABLE 1. DRC-10520 spECIFICAtIOns
Apply over temperature range power supply ranges reference voltage
and frequency range and 10% harmonic distortion in the reference.
pARAMEtER
REsOLUtIOn
ACCURACY AnD
DYnAMICs
Output Accuracy
Without Scott-T
With Scott-T P/N29305
Differential Linearity
Output Settling Time
DIGItAL InpUt/OUtpUt
Logic Type
Logic Voltage level
Load Current
Timing
REFEREnCE InpUt
Type
Voltage
Frequency
Input Impedance
Single Ended
Differential
AnALOG OUtpUt
Type
Output Current
Max Output Voltage (tracks
reference input voltage)
Scale Factor Variation
DC Offset (each line to
ground)
Protection
VALUE
16 bits
NOTES for Table 1:
1) 700ma per P/S is in relationship to driving torque loads. Large step
torque loads can cause converter to pull max current. For these conditions
the converter seat sink protection is very important. A solution to combat
large step torque loads is to convert the large steps in position change to
occur over smaller steps which will decrease peak P/S currents.
±1 or ±4 minutes
±10 minutes (1.5 VA min for CT load)
±16 minutes (2 VA min for CT load)
±1 LSB
Less than 40 µsec for any digital input
step change
Natural binary angle parallel positive logic
CMOS and TTL compatible.
Inputs are CMOS transient protected.
Logic 0 = 0 to +0.8 V
Logic 1 = 2 V to 1/3 of VDD + 10%
20 µA max (bit 1-16)
65 µA max (LL LM LA)
See Timing Diagram (FIGURES 2A&2B ).
(Note 2)
Differential 3.4 V rms
Higher voltages are scaled by adding
series resistors
DC to 1 kHz
13 kΩ ±0.5%
26 kΩ ±0.5%
Resolver
300 mA rms min (2 VA min) (NOTE 3)
6.8V rms max line-to-line ±1%
(SEE NOTE 2)
Simultaneous amplitude variation in all
output lines as function of digital angle is
±0.1% max.
±15 mV max varies with input angle.
Output is protected from overcurrent
short circuits and voltage feedback tran-
sients.
2) Output voltage can be scaled by lowering reference voltage. Factory
set for fixed factor of 2. Example: 3.4V Ref x 2 "scale factor" = 6.8V
Output.
3) Power calculation examples for SIN /COS 2VA total output power:
Example to calculate the load for SIN/COS 2VA as follows.
At 45°, Sin = Cos
2VA = 1VA (Sin) + 1VA (Cos)
SIN 45 = 0.707, COS 45 = 0.707
0.707 x (Output Voltage) 6.8V = 4.8 V
1VA/4.8V = .208A
4.8V/ .208A = 23 ohms (Load Impedance)
At 0°, 90°, 180°.... etc., when either sin or cos is maximum amplitude,
the maximum current for a 2 VA load is:
6.8V/ 23 ohms = .296A
Example for 80°
The load impedance is 23.1 ohms:
Sin dissipates 1.1808V * (1.1808V/23.1ohms) = .06VA
Cos dissipates 6.697V * (6.697V/23.1ohms) = 1.94VA
Total = 1.94 +0.06 = 2VA
At 90 degree,
sin=1, cos=0,
sin(90)*6.8*A=2VA
—>max current for sin signal=2/6.8=0.294A, no current for cos signal
Z=6.8/.294=23.1ohm
tECHnICAL InFORMAtIOn IntRODUCtIOn
The DRC-10520 is a digital-to-resolver (D/R) converter which has
an inherently high accuracy and low scale factor variation. The
circuit is based on an algorithm whose theoretical math error is
only ±3.5 arc seconds and whose theoretical scale factor varia-
tion with angle is less than ±0.015%. Therefore accuracy and
scale factor are limited only by the physical components, not by
the algorithm.
The digital inputs are CMOS double buffered transparent latches
(FIGURE 1). Angular output is determined by adding bits in the
logic 1 state.
pOWER sUppLIEs
Voltage
Voltage Limits
Max Voltage Without Damage
Current
Peak Current At Power Turn
On or Short Circuit (when
using Transformer)
tEMpERAtURE RAnGEs
Operating (-3xx)
(-1xx)
Storage
pHYsICAL
CHARACtERIstICs
Package Type
Size
Weight
+15V
+5%
+V
-V
20 V peak max
3 V above output
voltage min.
+18V
-18V
+25V
-25V
20 mA 20 mA load dependent
max
max
700 mA max (*See Note 1)
-15V
+5%
0°C to +70°C case
-55°C to +125°C case
-55°C to +135°C
32 pin triple DIP
1.14 x 1.74 x 0.18 inch (29 x 44 x 4 mm)
1.15 oz (33 g)
pOWER sUppLY CYCLInG
Power supply cycling of the DDC converter should follow the
guidelines below to avoid any potential problems. Strictly main-
DRC-10520
T-7/08-0
Data Device Corporation
www.ddc-web.com
3
tain proper sequencing of supplies and signals per typical
CMOS circuit guidelines:
- Apply power supplies first (+15, -15V and ground).
- Apply digital control signals next.
- Apply analog signals last.
The reverse sequence should be followed during power down of
the circuit.
scaled by calculating the value of the scaling resistor with the
following equation:
R
REF
INPUT
REF
R
R
R REF
H
L
DRC-10520
REFEREnCE LEVEL ADJUstMEnt
R
REF
The input is specified for operation at a reference level of 3.4V
rms; however, reference levels other than 3.4V rms may be
(V
REF
- 3.4)
= _______ x 13k
3.4
eg., if V
REF
= 26 V rms, then R
REF
(26 - 3.4)
= ______ x 13k
3.4
200 nS min.
TRANSPARENT
LATCHED
DATA 1-16 BITS
125 nS min.
With LA set Lo = 125 nS min.
With LL, LM, LA tied together = 200 nS min.
Data Changing
Data Stable
FIGURE 2A. LL, LM, LA tIMInG DIAGRAM (16 BIt)
LA
200 nS min.
200 nS min.
200 nS min.
LM
Bits (1-8)
200 nS min.
LL
Bits (9-16)
DATA
125 nS min.
125 nS min.
125 nS min.
125 nS min.
LA, LM, LL
Transparent = Hi
Latched = Lo
Data Changing
Data Stable
FIGURE 2B. LL, LM, LA tIMInG DIAGRAM (8 BIt)
Data Device Corporation
www.ddc-web.com
4
DRC-10520
T-7/08-0
The output is 6.8V rms line-to-line resolver format signal which
may be converted into a synchro format of 11.8V Iine-to-line with
the companion Scott-T transformer module available as DDC P/N
29305.
sin = (R -R ) A [1 + A (θ)] sin
θ
cos = (R -R ) A [1 + A (θ)] cos
θ
h
l
o
h
l
o
DRIVInG tHE pOWER AMpLIFIER WItH tHE
REFEREnCE
The high power amplifier stage can be driven by a standard ±15V
DC supply or with a high efficiency pulsating power supply derived
from the reference voltage source. A companion power trans-
former DDC P/N 29306, designed to implement the pulsating
power source for the DRC-10520, is also available (FIGURE 3).
The DRC-10520 will not be damaged by sequencing order in the
±15V, V
L
supplies or the reference input.
The output amplifiers simultaneously track reference voltage
fluctuations because they are proportional to (R
H
-R
L
). The ampli-
tude factor A
O
is 2 for 6.8V rms L-L output. The maximum varia-
tion in A
O
from all causes is 0.3%. The term A (θ) represents the
variation of the amplitude with the digital input angle. A (θ), which
is called the scale factor variation, is a smooth function of
θ
with-
out discontinuities and is less than ±0.1% for all values of
θ.
The
total maximum variation in A
O
[1 + A (θ)] is therefore ±0.4%.
Because the amplitude factor (R
H
-R
L
) A
O
[1 + A (θ)] varies simul-
taneously on all output lines, it will not be a source of error when
the DRC-10520 is to drive a ratiometric system such as a resolv-
er or synchro. However, if the outputs are used independently, as
in x-y plotters, the amplitude variations must be taken into
account.
OUtpUt pROtECtIOn AnD BIt
The output is protected from overcurrent, short circuits and volt-
age feedback transients. The BIT circuit detects overcurrent
conditions in the sine or cosine resolver output. A logic “0” is used
for overcurrent detection. Normal operation is logic “1.” The BIT
line is normally at logic “1.” An overload or short circuit will cause
the BIT line to drop after 1 sec when the output current exceeds
a peak level of approximately 450 mA.
tABLE 2. pIn COnnECtIOns
pIn
1
2
3
4
5
6
7
8
9
10
11
FUnCtIOn
N.C.
N.C.
16 (LSB)
COS
SIN
+V
-V
1 (MSB)
2
3
4
pIn
12
13
14
15
16
17
18
19
20
21
22
FUnCtIOn
5
6
7
8
LM
LL
9
10
11
12
13
pIn
23
24
25
26
27
28
29
30
31
32
FUnCtIOn
14
R
l
R
h
15
-15 V
GND
LA
+15 V
BIT
N.C.
OUtpUt pHAsInG AnD OUtpUt sCALE FACtOR
The analog output signals have the following phasing:
6
3.4 Vrms
1
REFERENCE
SOURCE
400 Hz
7
3
21.6 Vrms
C.T.
4
RL
C-1
+
+V
RH
+SIN
1
6.8 Vrms
2
6
S
1
2
DRC-10520
GND
+COS
(SYNCHRO ONLY)
T-1
29306
33920
5
D1
D4
D2
D3
35 V DC
+
C-2
5
S
8
4
-V
(RESOLVER
ONLY)
3
T-2
R 7
S
3
S
4
S
2
PARTS LIST FOR 400 Hz
For T1 and T2 see Ordering Information
D1, D2, D3, and D4 = 1N4245
C-1 and C-2 = 22 µF, 35 V DC capacitor
DIGITAL INPUT
29305
32976
*29947 RESOLVER
±15 V
FIGURE 3. tYpICAL COnnECtIOn DIAGRAM UtILIzInG pULsAtInG
pOWER sOURCE FOR sYnCHRO OUtpUt
Data Device Corporation
www.ddc-web.com
5
DRC-10520
T-7/08-0
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