R7FS124773A01CNE datasheet, PDF

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R7FS124773A01CNE: DescriptionRISC MICROCONTROLLER; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，98 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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R7FS124773A01CNE Overview

RISC MICROCONTROLLER

R7FS124773A01CNE Parametric

Parameter Name	Attribute value
package instruction	HVQCCN,
Reach Compliance Code	compli
Has ADC	YES
Address bus width
bit size	32
maximum clock frequency	20 MHz
DMA channel	YES
External data bus width
length	7 mm
Number of I/O lines	35
Number of terminals	48
PWM channel	YES
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
speed	32 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	2.4 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
width	7 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC
Base Number Matches	1

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Features

S124 MCU (Ultra-Low-Power MCU)

32-bit ARM

Cortex

-M0+ microcontroller

Ultra-low power 32-MHz ARM

Cortex

-M0+ microcontroller, up to 128-KB code flash memory, 16-KB SRAM,

Capacitive Touch Sensing Unit, 14-bit A/D Converter, 12-bit D/A Converter, security and safety features.

Features

■

ARM Cortex-M0+ Core



ARMv6-M architecture

Maximum operating frequency: 32 MHz

Debug and Trace: DWT, BPU, CoreSight™ MTB-M0+

CoreSight Debug Port: SW-DP

Up to 128-KB code flash memory

4-KB data flash memory (up to 100,000 erase/write cycles)

Up to 16-KB SRAM

128-bit unique ID

■

System and Power Management



Low-power modes

RealTime Clock (RTC)

Event Link Controller (ELC)

Data Transfer Controller (DTC)

Key Interrupt Function (KINT)

Power-on reset

Low Voltage Detection with voltage settings

■

Memory



■

Security and Encryption

■

Connectivity



AES128/256



True Random Number Generator (TRNG)



Capacitive Touch Sensing Unit (CTSU)



Main clock oscillator (MOSC)

(1 to 20 MHz when VCC = 2.4 to 5.5 V)

(1 to 8 MHz when VCC = 1.8 to 5.5 V)

(1 to 4 MHz when VCC = 1.6 to 5.5 V)



Sub-clock oscillator (SOSC) (32.768 kHz)



High-speed on-chip oscillator (HOCO)

(24, 32, 48, 64 MHz when VCC = 2.4 to 5.5 V)

(24, 32, 48 MHz when VCC = 1.8 to 5.5 V)

(24, 32 MHz when VCC = 1.6 to 5.5 V)



Middle-speed on-chip oscillator (MOCO) (8 MHz)



Low-speed on-chip oscillator (LOCO) (32.768 kHz)



Independent watchdog timer OCO (15 kHz)



Clock trim function for HOCO/MOCO/LOCO



Clock out support



Up to 51 input/output pins

- Up to 3 CMOS input

- Up to 48 CMOS input/output

- Up to 6 5-V tolerant input/output (when VCC = 3.6 V)

- Up to 16 pins high current (20 mA)



VCC: 1.6 to 5.5 V



USB 2.0 Full-Speed Module (USBFS)

- On-chip transceiver with voltage regulator

- Compliant with USB Battery Charging Specification 1.2



Serial Communications Interface (SCI) × 3

- UART

- Simple IIC

- Simple SPI



Serial Peripheral Interface (SPI) × 2



C bus interface (IIC) × 2



CAN module (CAN)



14-Bit A/D Converter (ADC14)

12-Bit D/A Converter (DAC12)

Low-Power Analog Comparator (ACMPLP) × 2

Temperature Sensor (TSN)

General PWM Timer 32-Bit (GPT32)

General PWM Timer 16-Bit (GPT16) × 6

Asynchronous General-Purpose Timer (AGT) × 2

Watchdog Timer (WDT)

SRAM Parity Error Check

Flash Area Protection

ADC self-diagnosis function

Clock Frequency Accuracy Measurement Circuit (CAC)

Cyclic Redundancy Check (CRC) Calculator

Data Operation Circuit (DOC)

Port Output Enable for GPT (POEG)

Independent Watchdog Timer (IWDT)

GPIO Readback Level Detection

Main Oscillator Stop Detection

■

Human Machine Interface (HMI)

■

Multiple Clock Sources

■

Analog

■

Timers

■

General Purpose I/O Ports

■

Safety

■

Operating Voltage

■

Operating Temperature and Packages



Ta = –40°C to +85°C

- 36-pin LGA (4 mm × 4 mm, 0.5 mm pitch)



Ta = –40°C to +105°C

- 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)

- 48-pin LQFP (7 mm × 7 mm, 0.5 mm pitch)

- 64-pin QFN (8 mm × 8 mm, 0.4 mm pitch)

- 48-pin QFN (7 mm × 7 mm, 0.5 mm pitch)

- 40-pin QFN (6 mm × 6 mm, 0.5 mm pitch)

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S124

Table 1.3

Feature

Low Voltage Detection (LVD)

1. Overview

System (2/2)

Functional description

The Low Voltage Detection (LVD) monitors the voltage level input to the VCC pin and the

detection level can be selected using a software program. See section 7, Low Voltage

Detection (LVD) in User's Manual.



Main clock oscillator (MOSC)



Sub-clock oscillator (SOSC)



High-speed on-chip oscillator (HOCO)



Middle-speed on-chip oscillator (MOCO)



Low-speed on-chip oscillator (LOCO)



Independent Watchdog Timer on-chip oscillator



Clock out support.

See section 8, Clock Generation Circuit in User's Manual.

The clock frequency accuracy measurement circuit (CAC) is used to check the system clock

frequency with a reference clock signal by counting the number of pulses of the system clock

to be measured. The reference clock can be provided externally through a CACREF pin or

internally from various on-chip oscillators.

Event signals can be generated when the clock does not match or measurement ends.

This feature is particularly useful in implementing a fail-safe mechanism for home and

industrial automation applications.

See section 9, Clock Frequency Accuracy Measurement Circuit (CAC) in User's Manual.

The MCU has several functions for reducing power consumption, such as setting clock

dividers, stopping modules, selecting power control mode in normal operation, and

transitioning to low power modes. See section 10, Low Power Modes in User's Manual.

The Register Write Protection function protects important registers from being overwritten due

to software errors. See section 11, Register Write Protection in User's Manual.

The Watchdog Timer (WDT) is a 14-bit down-counter. It can be used to reset the MCU when

the counter underflows because the system has run out of control and is unable to refresh the

WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. The

refresh-permitted period can be set to refresh the counter and used as the condition to detect

when the system runs out of control. See section 22, Watchdog Timer (WDT) in User's Manual.

The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be

serviced periodically to prevent counter underflow. The IWDT provides functionality to reset

the MCU or to generate a non-maskable interrupt/interrupt for a timer underflow. Because the

timer operates with an independent, dedicated clock source, it is particularly useful in returning

the MCU to a known state as a fail safe mechanism when the system runs out of control. The

watchdog timer can be triggered automatically on reset, underflow, or refresh error, or by a

refresh of the count value in the registers. See section 23, Independent Watchdog Timer

(IWDT) in User's Manual.

Clock

Clock Frequency Accuracy

Measurement Circuit (CAC)

Low Power Mode

Watchdog Timer (WDT)

Independent Watchdog Timer (IWDT)

Table 1.4

Feature

Interrupt Control

Functional description

The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC

module. The ICU also controls NMI interrupts. See section 12, Interrupt Controller Unit (ICU) in

User's Manual.

Interrupt Controller Unit (ICU)

Table 1.5

Feature

Event Link

Functional description

The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral

modules as event signals to connect them to different modules, enabling direct interaction

between the modules without CPU intervention. See section 15, Event Link Controller (ELC) in

User's Manual.

Event Link Controller (ELC)

Table 1.6

Feature

Direct memory access

Functional description

The MCU incorporates a Data Transfer Controller (DTC) that performs data transfers when

activated by an interrupt request. See section 14, Data Transfer Controller (DTC) in User's

Manual.

Data Transfer Controller (DTC)

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S124

1. Overview

Table 1.7

Feature

Timers

Functional description

The General PWM Timer (GPT) is a 32-bit timer with 1 channel and a 16-bit timer with 6

channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or

the up- and down-counter. In addition, PWM waveforms for controlling brushless DC motors

can be generated. The GPT can also be used as a general-purpose timer. See section 19,

General PWM Timer (GPT) in User's Manual.

Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT)

output pins in the output disable state. See section 18, Port Output Enable for GPT (POEG) in

User’s Manual.

The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse

output, external pulse width or period measurement, and counting external events.

This 16-bit timer consists of a reload register and a down-counter. The reload register and the

down-counter are allocated to the same address, and they can be accessed with the AGT

The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count

mode, that are used by switching register settings.

For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and

automatically adjusts dates for leap years.

For binary count mode, the RTC counts seconds and retains the information as a serial value.

Binary count mode can be used for calendars other than the Gregorian (Western) calendar.

See section 21, Realtime Clock (RTC) in User's Manual.

General PWM Timer (GPT)

Port Output Enable for GPT (POEG)

Asynchronous General Purpose

Timer (AGT)

Realtime Clock (RTC)

Table 1.8

Feature

Communication interfaces (1/2)

Functional description

The Serial Communication Interface (SCI) is configurable to five asynchronous and

synchronous serial interfaces:



Asynchronous interfaces (UART and asynchronous communications interface adapter

(ACIA))



8-bit clock synchronous interface



Simple IIC (master-only)



Simple SPI



Smart card interface

The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and

transmission protocol.

SCI0 has FIFO buffers to enable continuous and full-duplex communication, and the data

transfer speed can be configured independently using an on-chip baud rate generator. See

section 25, Serial Communications Interface (SCI) in User's Manual.

The MCU has a two-channel I

C bus interface (IIC).

The IIC module conforms with and provides a subset of the NXP I

C bus (Inter-Integrated

Circuit bus) interface functions. See section 26, I

C Bus Interface (IIC) in User's Manual.

The MCU includes two independent channels of the Serial Peripheral Interface (SPI). The SPI

channels are capable of high-speed, full-duplex synchronous serial communications with

multiple processors and peripheral devices. See section 28, Serial Peripheral Interface (SPI) in

User's Manual.

The Controller Area Network (CAN) module provides functionality to receive and transmit data

using a message-based protocol between multiple slaves and masters in electromagnetically

noisy applications.

The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports

up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox

and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are

supported. See section 27, Controller Area Network (CAN) Module in User's Manual.

Serial Communications Interface

(SCI)

C Bus interface (IIC)

Serial Peripheral Interface (SPI)

Controller Area Network (CAN)

Module

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S124

Table 1.8

Feature

USB 2.0 Full-Speed Module (USBFS)

1. Overview

Communication interfaces (2/2)

Functional description

The MCU incorporates a USB 2.0 Full-Speed module (USBFS). The USBFS is a USB

controller that is equipped to operate as a device controller. The module supports full-speed

and low-speed transfer as defined in the Universal Serial Bus Specification 2.0. The module

has an internal USB transceiver and supports all of the transfer types defined in the Universal

Serial Bus Specification 2.0.

The USB has buffer memory for data transfer, providing a maximum of 5 pipes. PIPE0 and

PIPE4 to PIPE7 can be assigned any endpoint number based on the peripheral devices used

for communication or based on the user system.

The MCU supports revision 1.2 of the battery charging specification. Because the MCU can be

powered at 5 V, the USB LDO regulator provides the internal USB transceiver power supply

3.3 V. See section 24, USB 2.0 Full-Speed Module (USBFS) in User's Manual.

Table 1.9

Feature

Analog

Functional description

The MCU incorporates up to one unit of a 14-bit successive approximation A/D converter. Up

to 18 analog input channels are selectable. Temperature sensor output and internal reference

voltage are selectable for conversion. The A/D conversion accuracy is selectable from 12-bit

and 14-bit conversion making it possible to optimize the tradeoff between speed and resolution

in generating a digital value. See section 30, 14-Bit A/D Converter (ADC14) in User's Manual.

The MCU includes a 12-bit D/A converter with an output amplifier. See section 31, 12-Bit D/A

Converter (DAC12) in User's Manual.

The on-chip Temperature Sensor can be used to determine and monitor the die temperature

for reliable operation of the device. The sensor outputs a voltage directly proportional to the die

temperature, and the relationship between the die temperature and the output voltage is linear.

The output voltage is provided to the ADC for conversion and can be further used by the end

application. See section 32, Temperature Sensor (TSN) in User's Manual.

Analog comparators can be used to compare a reference input voltage and analog input

voltage. The comparison result can be read by software and also be output externally. The

reference input voltage can be selected from either an input to the CMPREFi (i = 0, 1) pin or

from the internal reference voltage (Vref) generated internally in this MCU.

The ACMPLP response speed can be set before starting an operation. Setting high-speed

mode decreases the response delay time, but increases current consumption. Setting low-

speed mode increases the response delay time, but decreases current consumption. See

section 33, Low-Power Analog Comparator (ACMPLP) in User's Manual.

14-bit A/D Converter (ADC14)

12-bit D/A Converter (DAC12)

Temperature Sensor (TSN)

Low-Power Analog Comparator

(ACMPLP)

Table 1.10

Feature

Human machine interfaces

Functional description

A key interrupt can be generated by setting the Key Return Mode register (KRM) and inputting

a rising/falling edge to the key interrupt input pins. See section 17, Key Interrupt Function

(KINT) in User's Manual.

The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the

touch sensor. Changes in the electrostatic capacitance are determined by software, which

enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode

surface of the touch sensor is usually enclosed with an electrical conductor so that a finger

does not come into direct contact with the electrode. See section 34, Capacitive Touch

Sensing Unit (CTSU) in User's Manual.

Key Interrupt Function (KINT)

Capacitive Touch Sensing Unit

(CTSU)

Table 1.11

Feature

Data processing

Functional description

The Cyclic Redundancy Check (CRC) generates CRC codes to detect errors in the data. The

bit order of CRC calculation results can be switched for LSB first or MSB first communication.

Additionally, various CRC generation polynomials are available. The snoop function allows

monitoring reads from and writes to specific addresses. This function is useful in applications

that require CRC code to be generated automatically in certain events, such as monitoring

writes to the serial transmit buffer and reads from the serial receive buffer. See section 29,

Cyclic Redundancy Check (CRC) Calculator in User's Manual.

Cyclic Redundancy Check (CRC)

Calculator

R01DS0264EU0100 Rev.1.00

Feb 23, 2016

Page 5 of 95

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