1.2 GHz Clock Distribution IC, 1.6 GHz Inputs,
Dividers, Delay Adjust, Five Outputs
AD9512
FEATURES
Two 1.6 GHz, differential clock inputs
5 programmable dividers, 1 to 32, all integers
Phase select for output-to-output coarse delay adjust
3 independent 1.2 GHz LVPECL outputs
Additive output jitter 225 fs rms
2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs
Additive output jitter 275 fs rms
Fine delay adjust on 1 LVDS/CMOS output
Serial control port
Space-saving 48-lead LFCSP
FUNCTIONAL BLOCK DIAGRAM
VS
GND
RSET
VREF
FUNCTION
SYNCB,
RESETB
PDB
DETECT
SYNC
AD9512
PROGRAMMABLE
DIVIDERS AND
PHASE ADJUST
/1, /2, /3... /31, /32
SYNC
STATUS
SYNC
STATUS
DSYNC
DSYNCB
LVPECL
OUT0
OUT0B
LVPECL
OUT1
OUT1B
LVPECL
OUT2
OUT2B
LVDS/CMOS
OUT3
OUT3B
LVDS/CMOS
/1, /2, /3... /31, /32
CLK1
CLK1B
/1, /2, /3... /31, /32
CLK2
CLK2B
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
/1, /2, /3... /31, /32
SCLK
SDIO
SDO
CSB
SERIAL
CONTROL
PORT
/1, /2, /3... /31, /32
Δ
T
DELAY
ADJUST
OUT4
OUT4B
05287-001
Figure 1.
GENERAL DESCRIPTION
The AD9512 provides a multi-output clock distribution in a
design that emphasizes low jitter and low phase noise to
maximize data converter performance. Other applications with
demanding phase noise and jitter requirements can also benefit
from this part.
There are five independent clock outputs. Three outputs are
LVPECL (1.2 GHz), and two are selectable as either LVDS
(800 MHz) or CMOS (250 MHz) levels.
Each output has a programmable divider that may be bypassed
or set to divide by any integer up to 32. The phase of one clock
output relative to another clock output may be varied by means
of a divider phase select function that serves as a coarse timing
adjustment.
One of the LVDS/CMOS outputs features a programmable
delay element with a range of up to 10 ns of delay. This fine
tuning delay block has 5-bit resolution, giving 32 possible delays
from which to choose.
The AD9512 is ideally suited for data converter clocking
applications where maximum converter performance is
achieved by encode signals with subpicosecond jitter.
The AD9512 is available in a 48-lead LFCSP and can be
operated from a single 3.3 V supply. The temperature range is
−40°C to +85°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2005 Analog Devices, Inc. All rights reserved.
AD9512
TABLE OF CONTENTS
Specifications..................................................................................... 4
Clock Inputs .................................................................................. 4
Clock Outputs ............................................................................... 4
Timing Characteristics ................................................................ 5
Clock Output Phase Noise .......................................................... 7
Clock Output Additive Time Jitter........................................... 10
Serial Control Port ..................................................................... 12
FUNCTION Pin ......................................................................... 13
SYNC Status Pin ......................................................................... 13
Power............................................................................................ 14
Timing Diagrams............................................................................ 15
Absolute Maximum Ratings.......................................................... 16
Thermal Characteristics ............................................................ 16
ESD Caution................................................................................ 16
Pin Configuration and Function Descriptions........................... 17
Terminology .................................................................................... 19
Typical Performance Characteristics ........................................... 20
Functional Description .................................................................. 24
Overall.......................................................................................... 24
FUNCTION Pin ......................................................................... 24
RESETB: 58h<6:5> = 00b (Default)..................................... 24
SYNCB: 58h<6:5> = 01b ....................................................... 24
PDB: 58h<6:5> = 11b............................................................. 24
DSYNC and DSYNCB Pins....................................................... 24
Clock Inputs ................................................................................ 24
Dividers........................................................................................ 25
Setting the Divide Ratio ........................................................ 25
Setting the Duty Cycle ........................................................... 25
Divider Phase Offset .............................................................. 29
Delay Block.................................................................................. 30
Calculating the Delay............................................................. 30
Outputs ........................................................................................ 30
Power-Down Modes .................................................................. 31
Chip Power-Down or Sleep Mode—PDB........................... 31
Distribution Power-Down .................................................... 31
Individual Clock Output Power-Down............................... 31
Individual Circuit Block Power-Down................................ 31
Reset Modes ................................................................................ 31
Power-On Reset—Start-Up Conditions when
VS is Applied........................................................................... 31
Asynchronous Reset via the FUNCTION Pin ................... 31
Soft Reset via the Serial Port................................................. 31
Single-Chip Synchronization.................................................... 32
SYNCB—Hardware SYNC ................................................... 32
Soft SYNC—Register 58h<2>............................................... 32
Multichip Synchronization ....................................................... 32
Serial Control Port ......................................................................... 33
Serial Control Port Pin Descriptions....................................... 33
General Operation of Serial Control Port............................... 33
Framing a Communication Cycle with CSB ...................... 33
Communication Cycle—Instruction Plus Data ................. 33
Write ........................................................................................ 33
Read ......................................................................................... 34
The Instruction Word (16 Bits) ................................................ 34
MSB/LSB First Transfers ........................................................... 34
Register Map and Description ...................................................... 37
Summary Table........................................................................... 37
Register Map Description ......................................................... 39
Power Supply................................................................................... 43
Power Management ................................................................... 43
Applications..................................................................................... 44
Using the AD9512 Outputs for ADC Clock Applications.... 44
CMOS Clock Distribution ........................................................ 44
Rev. A | Page 2 of 48
AD9512
LVPECL Clock Distribution......................................................45
LVDS Clock Distribution...........................................................45
Power and Grounding Considerations and Power Supply
Rejection.......................................................................................45
Outline Dimensions........................................................................46
Ordering Guide ...........................................................................46
REVISION HISTORY
6/05—Rev. 0 to Rev. A
Changes to Features ..........................................................................1
Changes to General Description .....................................................1
Changes to Table 1 ............................................................................4
Changes to Table 3 ............................................................................5
Changes to Table 4 ............................................................................7
Changes to Table 5 and Table 6 .....................................................12
Changes to Table 7 ..........................................................................13
Changes to Figure 12 and Figure 14 to Figure 16 .......................21
Changes to Figure 17 Caption .......................................................22
Changes to Figure 23 ......................................................................23
Changes to Divider Phase Offset Section ....................................29
Changes to Chip Power-Down or Sleep Mode—PDB Section .31
Changes to Distribution Power-Down Section...........................31
Changes to Individual Clock Output Power-Down Section .....31
Changes to Individual Circuit Block Power-Down Section ......31
Changes to Soft Reset via the Serial Port Section .......................31
Changes to SYNCB—Hardware SYNC Section..........................32
Changes to Soft SYNC Register 58h<2> Section ........................32
Changes to Multichip Synchronization Section..........................32
Changes to Serial Control Port Section .......................................33
Changes to Serial Control Port Pin Descriptions Section .........33
Changes to General Operation of Serial
Control Port Section .......................................................................33
Added Framing a Communication Cycle with CSB Section ....33
Added Communication Cycle—Instruction Plus
Data Section.....................................................................................33
Changes to Write Section...............................................................33
Changes to Read Section................................................................34
Changes to Instruction Word (16 Bits) Section ..........................34
Changes to MSB/LSB First Transfers Section..............................34
Changes to Figure 32 and Figure 36 .............................................35
Added Figure 38; Renumbered Sequentially...............................36
Changes to Table 17 ........................................................................37
Changes to Table 18 ........................................................................39
Changes to Power Supply Section.................................................43
Changes to Power Management Section......................................43
4/05—Revision 0: Initial Version
Rev. A | Page 3 of 48
AD9512
SPECIFICATIONS
Typical (Typ) is given for V
S
= 3.3 V ± 5%; T
A
= 25°C, R
SET
= 4.12 kΩ, unless otherwise noted. Minimum (Min) and Maximum (Max)
values are given over full V
S
and T
A
(−40°C to +85°C) variation.
CLOCK INPUTS
Table 1.
Parameter
CLOCK INPUTS (CLK1, CLK2)
1
Input Frequency
Input Sensitivity
Input Level
Input Common-Mode Voltage, V
CM
Input Common-Mode Range, V
CMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
1
2
Min
0
Typ
Max
1.6
Unit
GHz
mV p-p
V p-p
V
V
mV p-p
kΩ
pF
Test Conditions/Comments
150
2
2
3
1.5
1.3
4.0
1.6
150
4.8
2
1.7
1.8
5.6
Jitter performance can be improved with higher slew
rates (greater swing).
Larger swings turn on the protection diodes and can
degrade jitter performance.
Self-biased; enables ac coupling.
With 200 mV p-p signal applied; dc-coupled.
CLK2 ac-coupled; CLK2B ac bypassed to RF ground.
Self-biased.
CLK1 and CLK2 are electrically identical; each can be used as either differential or single-ended input.
With a 50 Ω termination, this is −12.5 dBm.
3
With a 50 Ω termination, this is +10 dBm.
CLOCK OUTPUTS
Table 2.
Parameter
LVPECL CLOCK OUTPUTS
OUT0, OUT1, OUT2; Differential
Output Frequency
Output High Voltage (V
OH
)
Output Low Voltage (V
OL
)
Output Differential Voltage (V
OD
)
LVDS CLOCK OUTPUTS
OUT3, OUT4; Differential
Output Frequency
Differential Output Voltage (V
OD
)
Delta V
OD
Output Offset Voltage (V
OS
)
Delta V
OS
Short-Circuit Current (I
SA
, I
SB
)
CMOS CLOCK OUTPUTS
OUT3, OUT4
Output Frequency
Output Voltage High (V
OH
)
Output Voltage Low (V
OL
)
Min
Typ
Max
Unit
Test Conditions/Comments
Termination = 50 Ω to V
S
− 2 V
Output level 3Dh (3Eh) (3Fh)<3:2> = 10b
See Figure 14
V
S
− 1.22
V
S
− 2.10
660
V
S
− 0.98
V
S
− 1.80
810
1200
V
S
− 0.93
V
S
− 1.67
965
MHz
V
V
mV
250
1.125
360
1.23
14
800
450
25
1.375
25
24
MHz
mV
mV
V
mV
mA
Termination = 100 Ω differential; default
Output level 40h (41h)<2:1> = 01b
3.5 mA termination current
See Figure 15
Output shorted to GND
Single-ended measurements;
B outputs: inverted, termination open
With 5 pF load each output; see Figure 16
@ 1 mA load
@ 1 mA load
250
V
S
− 0.1
0.1
MHz
V
V
Rev. A | Page 4 of 48
AD9512
TIMING CHARACTERISTICS
Table 3.
Parameter
LVPECL
Output Rise Time, t
RP
Output Fall Time, t
FP
PROPAGATION DELAY, t
PECL
, CLK-TO-LVPECL OUT
1
Divide = Bypass
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, LVPECL OUTPUTS
OUT1 to OUT0 on Same Part, t
SKP 2
OUT1 to OUT2 on Same Part, t
SKP2
OUT0 to OUT2 on Same Part, t
SKP2
All LVPECL OUT Across Multiple Parts, t
SKP_AB 3
Same LVPECL OUT Across Multiple Parts, t
SKP_AB3
LVDS
Min
Typ
Max
Unit
Test Conditions/Comments
Termination = 50 Ω to V
S
− 2 V
Output level 3Dh (3Eh) (3Fh)<3:2> = 10b
20% to 80%, measured differentially
80% to 20%, measured differentially
130
130
335
375
490
545
0.5
100
45
65
180
180
635
695
ps
ps
ps
ps
ps/°C
ps
ps
Ps
ps
ps
70
15
45
140
80
90
275
130
Output Rise Time, t
RL
Output Fall Time, t
FL
PROPAGATION DELAY, t
LVDS
, CLK-TO-LVDS OUT
1
OUT3 to OUT4
Divide = Bypass
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, LVDS OUTPUTS
OUT3 to OUT4 on Same Part, t
SKV2
All LVDS OUTs Across Multiple Parts, t
SKV_AB3
Same LVDS OUT Across Multiple Parts, t
SKV_AB3
CMOS
Output Rise Time, t
RC
Output Fall Time, t
FC
PROPAGATION DELAY, t
CMOS
, CLK-TO-CMOS OUT
1
Divide = Bypass
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, CMOS OUTPUTS
OUT3 to OUT4 on Same Part, t
SKC2
All CMOS OUT Across Multiple Parts, t
SKC_AB3
Same CMOS OUT Across Multiple Parts, t
SKC_AB3
LVPECL-TO-LVDS OUT
Output Skew, t
SKP_V
LVPECL-TO-CMOS OUT
Output Skew, t
SKP_C
LVDS-TO-CMOS OUT
Output Skew, t
SKV_C
200
210
350
350
ps
ps
Termination = 100 Ω differential
Output level 40h (41h) <2:1> = 01b
3.5 mA termination current
20% to 80%, measured differentially
80% to 20%, measured differentially
Delay off on OUT4
0.99
1.04
1.33
1.38
0.9
1.59
1.64
ns
ns
ps/°C
Delay off on OUT4
ps
ps
ps
ps
ps
ns
ns
ps/°C
Delay off on OUT4
B outputs are inverted; termination = open
20% to 80%; C
LOAD
= 3 pF
80% to 20%; C
LOAD
= 3 pF
Delay off on OUT4
−85
+270
450
325
681
646
865
992
1.71
1.76
1.02
1.07
1.39
1.44
1
+145
−140
+300
650
500
1.14
1.43
506
ps
ps
ns
ns
ps
Everything the same; different logic type
LVPECL to LVDS on same part
Everything the same; different logic type
LVPECL to CMOS on same part
Everything the same; different logic type
LVDS to CMOS on same part
0.74
0.88
158
0.92
1.14
353
Rev. A | Page 5 of 48
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