DEMO MANUAL DC1500A
LTC2393-16/LTC2392-16/
LTC2391-16: 16-Bit,1Msps/
0.5Msps/0.25Msps
Low Noise ADCs
performance of the LTC2393-16 in both parallel and serial
modes and is intended to demonstrate recommended
grounding, component placement and selection, routing
and bypassing for this ADC. Also several suggested driver
circuits for the analog inputs will be presented.
Design files for this circuit board are available at www.
linear.com/demo.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
DESCRIPTION
The LTC
®
2393/LTC2392/LTC2391-16 are low noise high
speed ADCs with both parallel and serial outputs that
can operate from a single 5V supply. The following text
refers to the LTC2393-16 but applies to all three parts.
The only difference being the maximum sample rates. The
LTC2393-16 supports a large ±4.096V fully differential input
range. This makes it ideal for high performance applica-
tions that require maximum dynamic range. Demonstration
circuit 1500A provides the user a means of evaluating the
–9V
GND
9V
CLK_IN
1MHz MAX
(80MHz FOR SERIAL)
3.3V
P-P
MAX
A
IN–
0V TO 4.096V MAX
(NOT NEEDED UNLESS
U2 IS DISABLED)
TO
DC718
A
IN+
0V TO 4.096V MAX
dc1500a
F01
Figure 1. DC1500A Connection Diagram
Table 1
ASSEMBLY VERSION
DC1500A-A
DC1500A-B
DC1500A-C
PART NUMBER
LTC2393CLX-16
LTC2392CLX-16
LTC2391CLX-16
MAX CONVERSION RATE
1Msps
0.5Msps
0.25Msps
MAX PARALLEL CLK IN
FREQUENCY
1MHz
500kHz
250kHz
MAX SERIAL CLK IN
FREQUENCY
80MHz
40MHz
20MHz
dc1500af
1
DEMO MANUAL DC1500A
QUICK START PROCEDURE
Check to make sure that all switches and jumpers are
set as shown in the connection diagram of Figure 1. The
default connections configure the ADC for parallel op-
eration with the output data in offset binary format. The
analog input is AC-coupled and the internal reference of
the ADC is used.
Connect DC1500A to a DC718B/C USB High Speed Data
Collection Board using connector J1. Connect DC718B/C
to a host PC with a standard USB A/B cable. Apply ±9V
to the indicated terminals. Apply a low jitter signal source
to J3 (AIN
+
). The default setup uses a single ended to dif-
ferential converter so that it is only necessary to apply an
input signal to J3. Connect a low jitter 1MHz 3.3V
P-P
sine
wave or square wave to connector J2 (CLK). Note that J2
has a 50Ω termination resistor to ground.
Run the QuickEval-II software (Pscope.exe version K66
or later) supplied with DC718B/C or download it from
www.linear.com.
Complete software documentation is available from the
Help menu. Updates can be downloaded from the Tools
menu. Check for updates periodically as new features
may be added.
The Pscope software should recognize DC1500A and
configure itself automatically.
Click the Collect button (see Figure 6) to begin acquiring
data. The Collect button then changes to Pause, which
can be clicked to stop data acquisition.
SETUP
DC Power
DC1500A requires ±9VDC at approximately 100mA. Most
of the supply current is consumed by the CPLD, op amps,
regulators and discreet logic on the board. The ±9VDC
input voltage powers the ADC through LT1763 regulators
which provide protection against accidental reverse bias.
Additional regulators provide power for the CPLD and op
amps. See Figure 1 for connection details.
Clock Source
You must provide a low jitter 3.3V
P-P
sine or square wave
to J2. The clock input is AC-coupled so the DC level of the
clock signal is not important. A generator like the HP8644
or similar is recommended. Even a good generator can start
to produce noticeable jitter at low frequencies. Therefore
it is recommended for lower sample rates to divide down
a higher frequency clock to the desired sample rate. One
way to do this is by placing the ADC in the serial mode.
This can be accomplished by setting the SER/PARL posi-
tion of SW1 to the high position. In the serial mode the
ratio of clock frequency to conversion rate is 80:1. In
the parallel mode there is a 1:1 ratio of clock frequency
to conversion rate. If the clock input is to be driven with
logic, it is recommended that the 50Ω terminator (R17)
be removed. Slow rising edges may compromise SNR of
the converter in the presence of high amplitude higher
frequency input signals.
Data Output
Parallel data output from this board (0V to 3.3V default),
if not connected to DC718, can be acquired by a logic
analyzer, and subsequently imported into a spreadsheet, or
mathematical package depending on what form of digital
signal processing is desired. Alternatively, the data can be
fed directly into an application circuit. Use pin 3 of J1 to
latch the data. The data can be latched using either edge
of this signal. The data output signal levels at J1 can also
be reduced to 0V to 2.5V if the application circuit cannot
tolerate the higher voltage. This is accomplished by moving
JP7 to the 2.5V position.
Reference
JP4, JP5 and JP6 allow you to select an on chip refer-
ence or an external LT1790A-4.096 as the reference. The
worst case initial accuracy and drift specifications of the
external reference are better than the on chip reference.
To use the internal reference set JP6 to FLT, JP4 to ADC
and JP5 to REFIN. To use the LT1790A-4.096 set JP5 and
JP6 to GND and JP4 to EXT.
dc1500af
2
DEMO MANUAL DC1500A
SETUP
Analog Input
The default driver for the analog inputs of the LTC2393-16
on DC1500A is shown in Figure 2. This circuit converts a
single-ended 0V to 4.096V input signal applied at A
IN
into
a differential signal with a swing of ±4.096V between the
+IN and –IN inputs of the ADC. In addition this circuit band
limits the input frequencies to approximately 100kHz which
is the useful linear bandwidth of the LTC2393-16.
Alternatively, if your application circuit produces a dif-
ferential signal which can drive the ADC but you need to
level shift the input signal, the circuits of Figure 3 and
Figure 4 can be used. The circuit of Figure 3 AC-couples
the input signal and is usable down to about 10kHz. The
lower frequency limit can be extended by increasing C37
and C51. The circuit of Figure 3 can be implemented on
DC1500A by putting JP1 and JP3 in the AC position and
moving R2 and R3 to the R50 and R53 positions. At this
point it will be necessary to drive both A
IN+
and A
IN–
. One
of these RC pairs can be attached to the input of the circuit
in Figure 2. This allows a single-ended input signal to be
level shifted. This is the default condition for DC1500A.
One of the most asked for ADC driver circuits is one that
allows the input voltage to go below ground with a single
supply ADC. Figure 4’s input driver allows the input volt-
age range to go below ground. It DC-couples and level
shifts the analog input at the expense of attenuating the
input level by a factor of 2. The circuit of Figure 4 can be
implemented on DC1500A by setting V
CM
to External and
biasing the external pin to 4.096V. Then replace R1 and
R6 with 1k, put JP1 and JP3 in the DC position and move
R2 and R3 to the R50 and R53 positions.
R2
249Ω
A
IN
0V TO 4.096V
R51
49.9Ω
C2
0.002μF
NPO
R3
249Ω
R52
49.9Ω
Data Collection
For SINAD, THD or SNR testing a low noise, low distortion
generator such as the B&K Type 1051 or Stanford Research
DS360 should be used. A low jitter RF oscillator such as
the HP8644 is used as the clock source.
This demo board is tested in house by attempting to
duplicate the FFT plot shown on the front page of the
LTC2393-16 data sheet. This involves using a 1MHz clock
source, along with a sinusoidal generator at a frequency
of 20kHz. The input signal level is approximately –1dBfs.
The input is filtered with a 20kHz single pole RC filter
shown in Figure 5. The FFT shown in the data sheet is a
16384-point FFT. A typical FFT obtained with DC1500A is
shown in Figure 6. Note that to calculate the real SNR, the
signal level (F1 amplitude = –1.117dB) has to be added
back to the SNR that PScope displays. With the example
shown in Figure 6, this means that the actual SNR would
be 94.237dB instead of the 93.12dB that PScope displays.
Taking the RMS sum of the recalculated SNR and the THD
yields a SINAD of 93.68 dB which is fairly close to the
typical value for this ADC.
There are a number of scenarios that can produce
misleading results when evaluating an ADC. One that is
common is feeding the converter with a frequency, that
is a sub-multiple of the sample rate, and which will only
exercise a small subset of the possible output codes. The
proper method is to pick an M/N frequency for the input
sine wave frequency. N is the number of samples in the
FFT. M is a prime number between one and N/2. Multiply
M/N by the sample rate to obtain the input sine wave
frequency. Another scenario that can yield poor results
is if you do not have a signal generator capable of ppm
levels of frequency accuracy or if it cannot be slaved to the
clock frequency. You can use an FFT with windowing to
reduce the “leakage” or spreading of the fundamental, to
get a close approximation of the ADC performance. If an
amplifier or clock source with poor phase noise is used,
the windowing will not improve the SNR.
+
LT6350
+
LTC2393-16
–
–
V
CM
dc1500a
F02
C53
10μF
Figure 2. Single-Ended to Differential Driver
dc1500af
3
DEMO MANUAL DC1500A
SETUP
Layout
As with any high performance ADC, this part is sensitive
to layout. The area immediately surrounding the ADC on
DC1500A should be used as a guideline for placement,
and routing of the various components associated with the
ADC. Here are some things to remember when laying out
a board for the LTC2393-16. A ground plane is necessary
to obtain maximum performance. Keep bypass capaci-
tors as close to supply pins as possible. Use individual
low impedance returns for all bypass capacitors. Use of a
symmetrical layout around the analog inputs will minimize
the effects of parasitic elements. Shield analog input traces
with ground to minimize coupling from other traces. Keep
traces as short as possible.
V
CM
(PIN 36)
C37
10μF
A
IN
0V TO 4.096V
+
Component Selection
When driving a low noise, low distortion ADC such as
the LTC2393-16, component selection is important so
as to not degrade performance. Resistors should have
low values to minimize noise and distortion. Metal film
resistors are recommended to reduce distortion caused
by self heating. Because of their low voltage coefficients,
which can reduce distortion NPO or silver mica capacitors
should be used. Any buffer used to drive the LTC2393-16
should have low distortion, low noise and a fast settling
time such as the LT6350.
4.096V
R51
49.9Ω
R1
1k
R30
R50
1k
249Ω
R51
49.9Ω
R30
R50
1k
249Ω
+IN
(PIN 43)
V
CM
(PIN 36)
R37
1k
R53
249Ω
C2
2200pF
NPO
–IN
(PIN 42)
dc1500a
F03
A
IN
–4.096V
TO
4.096V
+
+IN
(PIN 43)
4.096V
R37
1k
R6
1k
R53
249Ω
C2
2200pF
NPO
–IN
(PIN 42)
dc1500a
F04
A
IN–
0V TO 4.096V
C51
10μF
R52
49.9Ω
A
IN–
–4.096V
TO
4.096V
R52
49.9Ω
Figure 3. AC-Coupled Differential Driver
Figure 4. DC-Coupled Differential Driver
FROM SINE
GENERATOR
TO J3
249Ω
0.033μF
dc1500a
F05
Figure 5. 20kHz RC Filter
dc1500af
4
DEMO MANUAL DC1500A
SETUP
Figure 6. Pscope Screenshot
MISCELLANEOUS DIP SWITCHES AND JUMPERS
Definitions
JP2:
V
CM
sets the DC bias for A
IN+
and A
IN–
when the
inputs are AC-coupled. INT is the default position.
SW1:
SER_PARL:
Selects serial or parallel operation. Default
position is parallel. In parallel mode f
S
= f
CLK
. In serial
mode f
S
= f
CLK
/80.
OB/2CL:
Selects offset binary or two’s complement data for-
mat for ADC output word. The default is offset binary.
CSL:
This pin must be kept low for normal operation.
RDL:
This pin must be kept low for normal operation.
dc1500af
5
京公网安备 11010802033920号
EEWORLD
