EEWORLDEEWORLDEEWORLD

Part Number

Search

531MA394M000BGR

Description
LVPECL Output Clock Oscillator, 394MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
Categoryoscillator   
File Size268KB,15 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

531MA394M000BGR Overview

LVPECL Output Clock Oscillator, 394MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531MA394M000BGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
Is SamacsysN
Other featuresTAPE AND REEL
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability50%
JESD-609 codee4
Manufacturer's serial number531
Installation featuresSURFACE MOUNT
Nominal operating frequency394 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVPECL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Base Number Matches1
S i 5 3 0 / 5 31
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.0 7/06
Copyright © 2006 by Silicon Laboratories
Si530/531
Where to start learning embedded systems
I have been working in hardware for more than a year after graduation and found that I am more interested in embedded systems. I hope that seniors who have studied embedded systems can give me some ad...
chenhong0203 Embedded System
The first post to test ArtCAM
[i=s]This post was last edited by deweyled on 2014-5-24 22:30[/i] Today I played around with the raw toolpath file in ArtCAM and carved a Chinese character "凤" (my wife's name has the word "凤", so I'm...
deweyled Creative Market
arm asm ldr problem
ldr r2, [r1], #4 Is it true that after execution, r1 += 4? Please let me know....
bravo314 ARM Technology
Phase Noise Analysis of Phase-Locked Loop Frequency Synthesizer
Abstract The phase noise of the frequency synthesizer directly affects the improvement factor of the moving target radar. This paper focuses on a comprehensive analysis of the phase noise of the phase...
JasonYoo Analog electronics
EEWORLD University Hall----Live Replay: Keysight High-Speed Bus PCIe5.0 Technology Development and Test Sharing
Live replay: Keysight high-speed bus PCIe5.0 technology development and test sharing : https://training.eeworld.com.cn/course/6168...
hi5 Integrated technical exchanges
CMSIS_RTOS_Tutorial self-translated Chinese version
[backcolor=white][color=#000000]I. Introduction[/color][/backcolor] [backcolor=white][color=#000000]This document is an excerpt from "The Designers Guide to the Cortex-M Processor Family" by Trevor Ma...
灞波儿奔 Microcontroller MCU

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 483  2252  2862  60  1899  10  46  58  2  39 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号