EEWORLDEEWORLDEEWORLD

Part Number

Search

DAPL15S667LF

Description
D Subminiature Connector, 15 Contact(s), Female, Wire Wrap Terminal, LEAD FREE
CategoryThe connector    The connector   
File Size175KB,1 Pages
ManufacturerAmphenol
Websitehttp://www.amphenol.com/
Environmental Compliance  
Download Datasheet Parametric View All

DAPL15S667LF Overview

D Subminiature Connector, 15 Contact(s), Female, Wire Wrap Terminal, LEAD FREE

DAPL15S667LF Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerAmphenol
package instructionLEAD FREE
Reach Compliance Codecompliant
Connector typeD SUBMINIATURE CONNECTOR
Contact to complete cooperationGOLD (16) OVER NICKEL
Contact completed and terminatedGOLD (16) OVER NICKEL
Contact point genderFEMALE
Contact materialCOPPER ALLOY
DIN complianceNO
empty shellNO
Filter functionNO
IEC complianceNO
insulator materialPOLYETHYLENE
JESD-609 codee4
MIL complianceNO
Manufacturer's serial numberDP
Plug informationMULTIPLE MATING PARTS AVAILABLE
Mixed contactsNO
Installation typeBOARD AND PANEL
OptionsGENERAL PURPOSE
Shell surfaceZINC
Shell materialSTEEL
Housing size2/A
Termination typeWIRE WRAP
Total number of contacts15
UL Flammability Code94V-0
C-DSUB-0067
6
PDM: Rev:F
STATUS:
Released
Printed: Aug 23, 2006
.
How does FPGA implement Hilbert transform?
I AD the beat echo signal of LFMCW radar and want to convert it into two IQ signals with a phase difference of 90°. Since the beat signal contains a frequency that is not single, I don't know how to u...
小二红 FPGA/CPLD
Ten ways for women to become "loved by men"
Ten ways for women to cultivate "love from men" Women don't have to be beautiful, but they must live beautifully; women don't have to be born smart, but they must develop intelligence; women don't hav...
花的世界 Talking
Detailed analysis of static in C language
I googled nearly three pages about static in C language, but found that there is very little information available. Some of them are long and incomprehensible, or they skip a few words at the key poin...
Aguilera DSP and ARM Processors
【Design Tools】Virtex-5 PCIE to DVI reference routine
DEMO is based on Virtex-5 LX110T to achieve PCIE to DVI conversion. After processing the input image, it is output ....
GONGHCU FPGA/CPLD
life
If we calculate based on normal working hours of 8 hours a day, what is the approximate lifespan of common IC chips (such as the 74LS series)?...
wy3168 FPGA/CPLD
What happened to my little program?
DELAY CLRWDT MOVLW 0x02 MOVWF TMP6 LOOPA MOVLW 0xFF MOVWF TMP7 DECFSZ TMP7,F GOTO $-1 BCF STATUS,Z DECFSZ TMP6,F GOTO LOOPA NOP END Why does the loop never end?...
mangomkt Embedded System

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1881  263  173  2528  1462  38  6  4  51  30 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号