74VHC595; 74VHCT595
8-bit serial-in/serial-out or parallel-out shift register with
output latches
Rev. 2 — 4 July 2012
Product data sheet
1. General description
The 74VHC595; 74VHCT595 are high-speed Si-gate CMOS devices and are pin
compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard No. 7A.
The 74VHC595; 74VHCT595 are 8-stage serial shift registers with a storage register and
3-state outputs. The shift registers have separate clocks.
Data is shifted on the positive-going transitions of the shift register clock input (SHCP).
The data in each register is transferred to the storage register on a positive-going
transition of the storage register clock input (STCP). If both clocks are connected together,
the shift register will always be one clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading.
It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The
storage register has 8 parallel 3-state bus driver outputs. Data in the storage register
appears at the output whenever the output enable input (OE) is LOW.
2. Features and benefits
Balanced propagation delays
All inputs have Schmitt-trigger action
Inputs accept voltages higher than V
CC
Input levels:
The 74VHC595 operates with CMOS input level
The 74VHCT595 operates with TTL input level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Applications
Serial-to-parallel data conversion
Remote control holding register
Nexperia
74VHC595; 74VHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74VHC595D
74VHCT595D
74VHC595PW
74VHCT595PW
74VHC595BQ
74VHCT595BQ
40 C
to +125
C
DHVQFN16
40 C
to +125
C
TSSOP16
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads; body
width 3.9 mm
Version
SOT109-1
Type number
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;
16 terminals; body 2.5
3.5
0.85 mm
SOT763-1
5. Functional diagram
14 DS
11 SHCP
10 MR
8-STAGE SHIFT REGISTER
Q7S
12 STCP
9
8-BIT STORAGE REGISTER
13 OE
3-STATE OUTPUTS
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
15 1
2
3
4
5
6
7
mna554
Fig 1.
Functional diagram
13
12
11
12
10
9
15
1
2
3
4
5
6
7
14
1D
11
R
C1/
SRG8
SHCP STCP
Q7S
Q0
Q1
Q2
14
DS
Q3
Q4
Q5
Q6
Q7
MR
10
OE
13
mna552
EN3
C2
2D
3
15
1
2
3
4
5
6
7
9
mna553
Fig 2.
74VHC_VHCT595
Logic symbol
Fig 3.
IEC logic symbol
©
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 4 July 2012
2 of 22
Nexperia
74VHC595; 74VHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
STAGE 0
DS
D
FF0
CP
SHCP
R
Q
D
STAGES 1 TO 6
Q
STAGE 7
D
FF7
CP
R
Q
Q7S
MR
D
Q
D
Q
LATCH
CP
STCP
OE
LATCH
CP
mna555
Q0
Q1 Q2 Q3 Q4 Q5 Q6
Q7
Fig 4.
Logic diagram
74VHC_VHCT595
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 4 July 2012
3 of 22
Nexperia
74VHC595; 74VHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
6. Pinning information
6.1 Pinning
74VHC595
74VHCT595
terminal 1
index area
Q2
16 V
CC
15 Q0
14 DS
13 OE
12 STCP
11 SHCP
10 MR
9
001aak048
74VHC595
74VHCT595
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
GND
Q7S
9
GND
(1)
16 V
CC
15 Q0
14 DS
13 OE
12 STCP
11 SHCP
10 MR
Q3
Q4
Q5
Q6
Q7
1
Q1
Q7S
001aak049
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration SO16 and TSSOP16
Fig 6.
Pin configuration DHVQFN16
6.2 Pin description
Table 2.
Symbol
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
Q7S
MR
SHCP
STCP
OE
DS
Q0
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
parallel data output 1
parallel data output 2
parallel data output 3
parallel data output 4
parallel data output 5
parallel data output 6
parallel data output 7
ground (0 V)
serial data output
master reset (active LOW)
shift register clock input
storage register clock input
output enable input (active LOW)
serial data input
parallel data output 0
supply voltage
74VHC_VHCT595
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 4 July 2012
4 of 22
Nexperia
74VHC595; 74VHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
7. Functional description
Table 3.
Control
SHCP STCP OE
X
X
X
X
X
X
L
L
H
L
MR
L
L
L
H
Function table
[1]
Input
DS
X
X
X
H
Output
Q7S
L
L
L
Q6S
Qn
NC
L
Z
NC
a LOW-level on MR only affects the shift registers
empty shift register loaded into storage register
shift register clear; parallel outputs in high-impedance OFF-state
logic HIGH-level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
Function
X
L
L
H
H
X
X
NC
Q6S
QnS
QnS
[1]
H = HIGH voltage state;
L = LOW voltage state;
= LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
DS
STCP
MR
OE
Q0
Q1
Z-state
Z-state
Q6
Q7
Q7S
Z-state
Z-state
Fig 7.
Timing diagram
74VHC_VHCT595
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 4 July 2012
5 of 22
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