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SSM6J503NU,LF(T

Description
MOSFET P CH 20V 6A 2-2AA1A
Categorysemiconductor    Discrete semiconductor   
File Size264KB,6 Pages
ManufacturerToshiba Semiconductor
Websitehttp://toshiba-semicon-storage.com/
Environmental Compliance
Download Datasheet Parametric View All

SSM6J503NU,LF(T Overview

MOSFET P CH 20V 6A 2-2AA1A

SSM6J503NU,LF(T Parametric

Parameter NameAttribute value
FET typeP channel
technologyMOSFET (metal oxide)
Drain-source voltage (Vdss)20V
Current - Continuous Drain (Id) at 25°C6A(Ta)
Drive voltage (maximum Rds On, minimum Rds On)1.5V,4.5V
Rds On (maximum value) when different Id, Vgs32.4 milliohms @ 3A, 4.5V
Vgs (th) (maximum value) when different Id1V @ 1mA
Gate charge (Qg) at different Vgs (maximum value)12.8nC @ 10V
Vgs (maximum value)±8V
Input capacitance (Ciss) at different Vds (maximum value)840pF @ 10V
FET function-
Power dissipation (maximum)1W(Ta)
Operating temperature150°C(TJ)
Installation typesurface mount
Supplier device packaging6-UDFNB(2x2)
Package/casing6-WDFN Exposed Pad
SSM6J503NU
TOSHIBA Field-Effect Transistor Silicon P-Channel MOS Type (U-MOSⅥ)
SSM6J503NU
Power Management Switch Applications
1.5V drive
Low ON-resistance: R
DS(ON)
= 89.6 mΩ (max) (@V
GS
= -1.5 V)
R
DS(ON)
= 57.9 mΩ (max) (@V
GS
= -1.8 V)
R
DS(ON)
= 41.7 mΩ (max) (@V
GS
= -2.5 V)
R
DS(ON)
= 32.4 mΩ (max) (@V
GS
= -4.5 V)
Unit: mm
Absolute Maximum Ratings
(Ta
=
25°C)
Characteristics
Drain-Source voltage
Gate-Source voltage
Drain current
DC
Pulse
Symbol
V
DSS
V
GSS
I
D
I
DP
(Note 1)
P
D
(Note 2)
t
≦10s
T
ch
T
stg
Rating
−20
±8
−6.0
-24.0
1
2
150
−55
to 150
Unit
V
V
A
Power Dissipation
Channel temperature
Storage temperature
W
°C
°C
Note:
UDFN6B
Using continuously under heavy loads (e.g. the application of
high temperature/current/voltage and the significant change in
JEDEC
temperature, etc.) may cause this product to decrease in the
JEITA
reliability significantly even if the operating conditions (i.e.
operating temperature/current/voltage, etc.) are within the
TOSHIBA
2-2AA1A
absolute maximum ratings.
Weight: 8.5 mg (typ.)
Please design the appropriate reliability upon reviewing the
Toshiba Semiconductor Reliability Handbook (“Handling
Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and
estimated failure rate, etc).
1,2,5,6: Drain
3: Gate
4: Source
Note 1: The pulse width limited by max channel temperature.
Note 2: Mounted on an FR4 board.
2
(25.4 mm
×
25.4 mm
×
1.6 mm, Cu Pad: 645 mm )
Marking(Top View)
6
5
4
Equivalent Circuit(Top View)
6
5
4
Pin Condition(Top View)
6
5
4
SP3
Drain
1
1
2
3
2
3
Source
1
2
3
Polarity marking
Polarity marking (on the top)
*Electrodes : on the bottom
Start of commercial production
2010-11
1
2014-03-01
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