PI3HDMI1310-A
HDMI™ Switch with non-blocking EQ Circuitry
Features
• Differential channel 3:1 Mux/DeMux for TDMS signals
• 3:1 Mux/DeMux for DDC signals
• non-EQ blocking circuitry to utilize ideal EQ found in
main receiver chipset
• Low power consumption to support Energy Star
Compliance
• Data rate support up to 3.4Gbps (16bit color depth per
channel)
• 2 pin control for port selection
• 3.3V power and 5V standby power
• ESD protection on all I/O pins
→ ±8kV contact per IEC61000-4-2
→ 7kV HBM per JESD22
• Packaging (Pb-free & Green): 72 - Contact TQFN
Description
Pericom Semiconductor’s PI3HDMI™ series of switch circuits
are targeted for high-resolution video networks that are based on
DVI/HDMI standards. The PI3HDMI1310-A is a 3-to-1 HDMI
Mux/DeMux Switch. It is designed for low bit-to-bit skew and
high channel-to-channel noise isolation. The maximum DVI/
HDMI data rate of 3.4Gbps provides the resolution required
by next generation HDTV and PC graphics. Three differential
channels are used for data (video signals for DVI or audio/video
signals for HDMI), and one differential channel is used for Clock
for decoding the TMDS signals at the outputs.
PI3HDMI1310-A was designed specifically to meet ATC-Sink
requirement for the HPD ports. The high speed video ports and
DDC ports can be either source or sink.
All TMDS I/O pins are protected with Pericom's ESD protection
circuits, supporting protection against ESD damage as high as
±8kV contact per IEC6000-4-2 spec.
Block Diagram
Pin Configuration (Top View)
VDD50
HPDC
HPDB
HPDA
D1+A
D0+A
D1-A
D0-A
GND
GND
D0-D3A±
D0-D3B±
D0-D3C±
4 - differential½
TMDS Lanes
4 - differential½
TMDS Lanes
4 - differential½
TMDS Lanes
4 - differential½
TMDS Lanes
D0-D3±
GND
D2-A
D2+A
D3-A
D3+A
VDD
1 72 71 70 69 68 67 66 65 64 63 62
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
GND
VDD
HPD_Sink
SEL2
SEL1
OE
VDD
D0-
D0+
GND
D1-
D1+
VDD
D2-
D2+
GND
D3-
D3+
VDD
DDC_Data
DDC_CLK
GND
GND
GND
GND
GND
DDC_CLK A
DDC_DATA A
DDC_CLK B
DDC_DATA B
DDC_CLK C
DDC_DATA C
DDC_CLK
DDC_DATA
D0-B
D0+B
D1-B
D1+B
D2-B
D2+B
VDD
D3-B
D3+B
HPD_A
HPD_B
HPD_C
100kΩ
HPD_Sink
GND
D0-C
D0+C
D1-C
D1+C
VDD
D2-C
D2+C
D3-C
D3+C
GND
Control Logic
26 27 28 29 30 31 32 33 34 35 36 37
DDC_DataA
DDC_CLKA
GND
GND
DDC_DataB
DDC_CLKB
VDD50
DDC_DataC
SEL1 SEL2
OE
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DDC_CLKC
GND
01/25/13
HDMI™ Switch with non-blocking EQ Circuitry
Pin Description
Pin #
69, 68, 71, 70,
3, 2, 5, 4,
8, 7, 10, 9, 12,
11, 15, 14
18, 17, 20, 19,
23, 22, 25, 24
65, 66, 67
33, 64
60
29, 28, 32, 31,
35, 34, 42, 43
55, 54, 53, 52,
51, 49, 48, 46,
45
58, 59
6, 13, 21, 44,
50, 56, 61
1, 16, 26, 27,
30, 36, 37, 38,
39, 40, 41, 53,
62, 63, 72
57
PI3HDMI1310-A
Pin Name
Dx±A (X = 0, 1, 2, 3)
Dx±B (X = 0, 1, 2, 3)
Dx±C (X = 0, 1, 2, 3)
Pin Type
I/O
I/O
I/O
Description
Port A High Speed inputs
Port B High Speed inputs
Port C High Speed inputs
HPD open-drain outputs for each port. Logic will follow
truth table on page 7.
External 1Kohm pull-up to 5V is required
5.0V voltage rail from HDMI/DVI connector. Used during
standby-mode.
GP I/O pin from SCALAR. Internal 100Kohm pull-down.
I2C signals for DDC communication on TMDS ports
4-differential high speed Output signals
Selection for D0-D3 and DDC signals (Select Pins, see truth
tables on page 5)
3.3V Power Supply
HPDA, HPDB, HPDC
VDD50
HPD_Sink
DDC_CLKx, DDC_Datax
DX± (x = 0, 1, 2, 3)
SEL1, SEL2
V
DD
Output
Power
Input
I/O
I/O
Inputs
Power
GND
Power
Ground.
Output enable (Active LOW). When HIGH, all outputs are
Hi-Z and chip is placed into Standby Mode. Under Standby
Mode, the current supply is from VDD50.
OE
Input
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HDMI™ Switch with non-blocking EQ Circuitry
PI3HDMI1310-A
BLOCK DIAGRAM EXPLANATION
DDC Switch Block
Passive NMOS based 3:1 mux for DDC channels from each HDMI/DVI input connector. This section can remain active even when
3.3V supply is gone, as long as 5.0V from TMDS connector is connected to the PI3HDMI1310-A IC.
3:1 High speed Differential Channel Block
4-differential channels per port. 3 channels are targeted for high speed data channels (250Mbps to 3.4Gbps) and 1 channel is
targeted for high speed clock signal (25MHz to 340MHz).
HPD Control Channels Block
Drives each HPD channels through the input pin, HPD_Sink.
This signal will need to drive external pull-down transistor circuit before connecting to the HDMI/DVI connector. The external
pull down circuit will look like the following:
5V
1KΩ
HPD
HPDA
5V
1KΩ
HPD
HPDB
5V
1KΩ
HPD
HPDC
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HDMI™ Switch with non-blocking EQ Circuitry
PI3HDMI1310-A
Truth table for D0-D3 and DDC Signals
SEL1
0
0
1
1
SEL2
0
1
0
1
Output Port
Port A
Port B
Port C
Hi-Z
Truth table for HPDx signals
Control Pins
OE
x
x
x
x
x
x
x
x
Hot Plug Detect Status
SEL1
L
L
L
L
H
H
H
H
SEL2
L
L
H
H
L
L
H
H
HPD_Sink HPD A
L
H
L
H
L
H
L
H
Hi-Z
L
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
HPD B
Hi-Z
Hi-Z
Hi-Z
L
Hi-Z
Hi-Z
Hi-Z
Hi-Z
HPD C
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
L
Hi-Z
Hi-Z
*All Hi-Z will become H if external pull-up connected at the output.
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ....................................................–65°C to +150°C
Supply Voltage to Ground Potential ...............................–0.5V to +4.0V
.
DC Input Voltage .............................................................. –0.5V to 4.0V
DC Output Current ...................................................................... 120mA
.
Power Dissipation ........................................................................... 0.5W
Note:
Stresses greater than those listed under MAXI-
MUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC Electrical Characteristics for Switching over Operating Range
(T
A
= –40°C to +85°C, V
DD
=
3.3V ±10%)
Parameter
VIH
VIL
VIK
(3)
Description
Input HIGH Voltage
Input LOW Voltage
Clamp Diode Voltage
Test Conditions
(1)
Guaranteed HIGH level
Guaranteed LOW level
V
DD
= Max., I
IN
= –18mA
Min
1.5
–0.5
Typ
(2)
Max
0.65
Units
V
–0.7
–1.2
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HDMI™ Switch with non-blocking EQ Circuitry
PI3HDMI1310-A
DC Electrical Characteristics for Switching over Operating Range
(T
A
= –40°C to +85°C, V
DD
=
3.3V ±10%)
Parameter
IIH
IIL
I
OFF
Description
Input HIGH Current
Input LOW Current
Off Leakage Current, for high
speed channels only
LVTTL Input HIGH Voltage
LVTTL Input LOW Voltage
Pull-down Resistance
Test Conditions
(1)
V
DD
= Max., V
IN
= V
DD
V
DD
= Max., V
IN
= GND
Vinput = 3.6V, V
DD
= 0V
Min
Typ
(2)
Max
±5
±5
50
Units
µA
Status Pins (HPD_SINK)
VIH
VIL
RP
2
GND
V
DD
50 = 5.0V
100k
5.3
0.8
V
Ohm
Power Supply Characteristics
Parameters
I
DD
I
DDQ
Description
Operating Power Supply Current
Standby Supply Current
Test Conditions
(1)
V
DD
= Max., V
SELx
= GND or
V
DD
OE - High
Min.
Typ.
(2)
6
3
Max.
10
5
Units
mA
Dynamic Electrical Characteristics Over the Operating Range (T
A
= -40º to +85ºC,
V
DD
= 3.3V ±10%, GND=0V)
Parameter
X
TALK
Description
Test Conditions
Min
Typ.
(2)
Max
Units
f= 1.13 GHz
See Fig. 3 for Measure-
Crosstalk on High Speed Channels
ment Setup
f = 825 MHz
OFF Isolation on High Speed
Channels
See Fig. 2 for Measure-
ment Setup
f = 825 MHz
DR = 1.54Gbps
f= 1.13 GHz
-34
-36
-28
-32
-1.5
-1.73
-1.82
-1.99
-2.08
3.0
GHz
0.4
V
dB
dB
O
IRR
I
LOSS
DR = 2.0Gbps
Differential Insertion Loss on High
DR = 2.25Gbps
Speed Channels (see figure 1)
DR = 3.0Gbps
DR = 3.4Gbps
-3dB BW for TMDS channels
TTL Low-level output voltage
I
OL
= 4mA
BW
V
OL(TTL)
Status Pins (HPD) - open drain output buffer
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
DD
= 3.3V, T
A
= 25°C ambient and maximum loading.
3. Substrate diode voltage drop. For testing reference.
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