74AVC16373DGG,118 datasheet, PDF

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74AVC16373DGG,118: DescriptionIC 16BIT D TRANSP LATCH 48TSSOP; Categorylogic logic; File Size205KB，15 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com

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74AVC16373DGG,118 Overview

IC 16BIT D TRANSP LATCH 48TSSOP

74AVC16373DGG,118 Parametric

Parameter Name	Attribute value
Brand Name	Nexperia
Maker	Nexperia
Parts packaging code	TSSOP
package instruction	TSSOP,
Contacts	48
Manufacturer packaging code	SOT362-1
Reach Compliance Code	compliant
Samacsys Description	74AVC16373 - 16-bit D-type transparent latch; 3.6 V tolerant; 3-state@en-us
series	AVC
JESD-30 code	R-PDSO-G48
JESD-609 code	e4
length	12.5 mm
Logic integrated circuit type	BUS DRIVER
Humidity sensitivity level	1
Number of digits	8
Number of functions	2
Number of ports	2
Number of terminals	48
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	9.4 ns
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	1.2 V
Nominal supply voltage (Vsup)	1.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	6.1 mm

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74AVC16373

Rev. 3 — 20 February 2018

16-bit D-type transparent latch; 3.6 V tolerant; 3-state

Product data sheet

General description

The 74AVC16373 is a 16-bit D-type transparent latch featuring separate D-type inputs

for each latch and 3-state outputs for bus oriented applications. One latch enable (LE)

input and one output enable (OE) input are provided per 8-bit section. The 74AVC16373

consist of two sections of eight D-type transparent latches with 3-state true outputs.

The 74AVC16373 is designed to have an extremely fast propagation delay and a

minimum amount of power consumption.

To ensure the high-impedance output state during power-up or power-down, pin nOE

should be tied to V

through a pull-up resistor (Live Insertion).

A dynamic controlled output (DCO) circuitry is implemented to support termination line

drive during transient (see

Figure 5).

Features and benefits

•

Wide supply voltage range from 1.2 V to 3.6 V

•

Complies with JEDEC standards:

–

JESD8-7 (1.2 V to 1.95 V)

–

JESD8-5 (1.8 V to 2.7 V)

–

JESD8-1A (2.7 V to 3.6 V)

•

CMOS low power consumption

•

Input/output tolerant up to 3.6 V

•

Dynamic Controlled Output (DCO) circuit dynamically changes output impedance,

resulting in noise reduction without speed degradation

•

Low inductance multiple V

and GND pins to minimize noise and ground bounce

•

Supports Live Insertion

Ordering information

Package

Temperature range Name

Description

plastic thin shrink small outline package;

48 leads; body width 6.1 mm

Version

SOT362-1

−40 °C to +85 °C

TSSOP48

Table 1. Ordering information

Type number

74AVC16373DGG

74AVC16373DGG,118 Related Products

	74AVC16373DGG,118	74AVC16373DGG,112	74AVC16373DGG,512	74AVC16373DGG,518
Description	IC 16BIT D TRANSP LATCH 48TSSOP	IC 16BIT D TRANSP LATCH 48TSSOP	74AVC16373 - 16-bit D-type transparent latch; 3.6 V tolerant; 3-state TSSOP 48-Pin	74AVC16373 - 16-bit D-type transparent latch; 3.6 V tolerant; 3-state TSSOP 48-Pin
Brand Name	Nexperia	Nexperia	Nexperia	Nexperia
Parts packaging code	TSSOP	TSSOP	TSSOP	TSSOP
package instruction	TSSOP,	TSSOP,	TSSOP,	TSSOP,
Contacts	48	48	48	48
Manufacturer packaging code	SOT362-1	SOT362-1	SOT362-1	SOT362-1
series	AVC	AVC	AVC	AVC
JESD-30 code	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48
JESD-609 code	e4	e4	e4	e4
length	12.5 mm	12.5 mm	12.5 mm	12.5 mm
Logic integrated circuit type	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER
Humidity sensitivity level	1	1	1	1
Number of digits	8	8	8	8
Number of functions	2	2	2	2
Number of ports	2	2	2	2
Number of terminals	48	48	48	48
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE
Output polarity	TRUE	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP	TSSOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260	260	260	260
propagation delay (tpd)	9.4 ns	9.4 ns	9.4 ns	9.4 ns
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	1.2 V	1.2 V	1.2 V	1.2 V
Nominal supply voltage (Vsup)	1.5 V	1.5 V	1.4 V	1.4 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	30	30
width	6.1 mm	6.1 mm	6.1 mm	6.1 mm

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