EEWORLDEEWORLDEEWORLD

Part Number

Search

531AA159M375DGR

Description
SINGLE FREQUENCY XO, OE PIN 1
CategoryPassive components   
File Size450KB,12 Pages
ManufacturerSilicon Laboratories Inc
Download Datasheet Parametric View All

531AA159M375DGR Online Shopping

Suppliers Part Number Price MOQ In stock  
531AA159M375DGR - - View Buy Now

531AA159M375DGR Overview

SINGLE FREQUENCY XO, OE PIN 1

531AA159M375DGR Parametric

Parameter NameAttribute value
typeXO (Standard)
frequency159.375MHz
Functionenable/disable
outputLVPECL
Voltage - Power3.3V
frequency stability±50ppm
Absolute pulling range (APR)-
Operating temperature-40°C ~ 85°C
Current - Power (maximum)121mA
grade-
Installation typesurface mount
Package/casing6-SMD, no leads
size/dimensions0.276" long x 0.197" wide (7.00mm x 5.00mm)
Height - Installation (maximum)0.071"(1.80mm)
Current - Power (disabled) (maximum)75mA
S i 5 3 0 / 5 31
R
EVISION
D
C
R YS TA L
O
SCILLATOR
(XO) (10 M H
Z
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
TO
1.4 GH
Z
)
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.5 6/18
Copyright © 2018 by Silicon Laboratories
Si530/531
Wake-up design of MSP430 and CC1101
[color=#333333][font=Verdana, Helvetica, Arial, sans-serif] With the rapid development of computer communication technology and the widespread application of the Internet, especially in the field of i...
Jacktang Microcontroller MCU
Talk about how to use MSP430 hardware I2C
[align=left]The hardware I2C controller is finally tuned out. In fact, the best reference material is still provided by TI. The code refers to the User's Guide and Application Note of MSP430. The IAR ...
Jacktang Microcontroller MCU
Intelligent motor development. Experts welcome.
Our company has just introduced a motor from abroad. Let us develop it... We can control this motor through USB, fieldbus (CAN bus), and Modbus. It seems that the PLC interface board of Saia from Swit...
makun Embedded System
Gas Discharge Tubes Help Protect VDSL Equipment and xDSL Splitters
Telecommunications equipment must be protected against threats posed by voltage/current surges and power failures as specified in the relevant standards. This protection can be achieved at the remote ...
LED123 Power technology
Ask about the MEMORYMAP problem when CCS3.1 software simulates C5402.
CMD程序如下: MEMORY {PAGE 0: EPROG:origin = 0x4000,len = 0xb000VECT:origin = 0xff80,len = 0x80PAGE 1: USERREGS: origin = 0x60,len = 0x1cBIOSREGS: origin = 0x7c,len = 0x4IDATA:origin = 0x80,len = 0x3f80EDA...
telemem DSP and ARM Processors
Implementation of Bluetooth protocol stack driver under Windows CE.pdf
Implementation of Bluetooth Protocol Stack Driver under Windows CE.pdf...
yuandayuan6999 MCU

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1229  1688  1020  1818  258  25  34  21  37  6 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号