OBSOLETE
MT4C4256(L)
256K x 4 DRAM
DRAM
FEATURES
• 512-cycle refresh in 8ms (MT4C4256) or 64ms
(MT4C4256 L)
• Industry-standard x4 pinout, timing, functions and
packages
• High-performance CMOS silicon-gate process
• Single +5V
±10%
power supply
• Low power, 0.8mW standby; 175mW active, typical
• All inputs, outputs and clocks are TTL-compatible
• FAST PAGE MODE access cycle
• Refresh modes:
/
R
?
A
/
S ONLY,
/
C
?
A
/
S-BEFORE-/R
?
AS (CBR),
/
HIDDEN and Extended (MT4C4256 L only)
• Low CMOS Standby Current, 200µA maximum
(MT4C4256 L)
256K x 4 DRAM
STANDARD OR LOW POWER,
EXTENDED REFRESH
PIN ASSIGNMENT (Top View)
20-Pin DIP
(DA-2)
DQ1
DQ2
WE
RAS
NC
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Vss
DQ4
DQ3
CAS
OE
A8
A7
A6
A5
A4
20-Pin ZIP
(DB-1)
OE
DQ3
Vss
DQ2
RAS
A0
A2
Vcc
A5
A7
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
CAS
DQ4
DQ1
WE
NC
A1
A3
A4
A6
A8
OPTIONS
• Timing
60ns access
70ns acces
80ns access
• Packages
Plastic DIP (300 mil)
Plastic SOJ (300 mil)
Plastic ZIP (350 mil)
• Version
512-cycle refresh in 8 ms
512-cycle refresh in 64 ms
MARKING
-6
-7
-8
None
DJ
Z
None
L
A3
Vcc
20/26-Pin SOJ
(DC-1)
DQ1
DQ2
WE
RAS
NC
1
2
3
4
5
26
25
24
23
22
Vss
DQ4
DQ3
CAS
OE
• Part Number Example: MT4C4256DJ-7 L
A0
A1
A2
A3
Vcc
9
10
11
12
13
18
17
16
15
14
A8
A7
A6
A5
A4
GENERAL DESCRIPTION
The MT4C4256(L) is a randomly accessed solid-state
memory containing 1,048,576 bits organized in a x4 configu-
ration. During READ or WRITE cycles, each bit is uniquely
addressed through the 18 address bits, which are entered 9
bits (A0 -A8) at a time.
/
R
?
A
/
S is used to latch the first 9 bits and
/
C
?
A
/
S the latter 9 bits. READ and WRITE cycles are selected
with the
?
W
/
E input. A logic HIGH on
?
W
/
E dictates READ
mode while a logic LOW on
?
W
/
E dictates WRITE mode.
During a WRITE cycle, data-in (D) is latched by the falling
edge of
?
W
/
E or
/
C
?
A
/
S, whichever occurs last. If
?
W
/
E goes LOW
MT4C4256(L)
REV. 4/94
prior to
/
C
?
A
/
S going LOW, the output pin(s) remain open
(High-Z) until the next
/
C
?
A
/
S cycle. If
?
W
/
E goes LOW after
data reaches the output pin, data-out (Q) is activated and
retains the selected cell data as long as
/
C
?
A
/
S remains LOW
(regardless of
?
W
/
E or
/
RA
/
S). This late
?
W
/
E pulse results in a
?
READ WRITE cycle. The four data inputs and four data
outputs are routed through four pins using common I/O
and pin direction is controlled by
?
W
/
E and
?
OE.
/
FAST PAGE MODE operations allow faster data opera-
tions (READ, WRITE or READ-MODIFY-WRITE) within a
row-address-defined (A0 -A8) page boundary. The FAST
PAGE MODE cycle is always initiated with a row-address
strobed-in by R
?
A
/
S followed by a column-address strobed-
/
1
Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
©1994,
Micron Semiconductor, Inc.
OBSOLETE
MT4C4256(L)
256K x 4 DRAM
in by
/
C
?
A
/
S.
/
C
?
A
/
S may be toggled-in by holding
/
R
?
A
/
S LOW
and strobing-in different column-addresses, thus execut-
ing faster memory cycles. Returning
/
R
?
A
/
S HIGH terminates
the FAST PAGE MODE cycle.
Returning
/
R
?
A
/
S and
/
C
?
A
/
S HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during the
/
R
?
A
/
S HIGH time. Memory cell data is retained in its correct
state by maintaining power and executing any R
?
A
/
S cycle
/
(READ, WRITE) or
/
R
?
A
/
S REFRESH cycle (/R
?
A
/
S ONLY, CBR,
or HIDDEN) so that all 512 combinations of
/
R
?
A
/
S addresses
(A0-A8) are executed at least every 8ms for the MT4C4256
and every 64ms for the MT4C4256 L, regardless of sequence.
The CBR REFRESH cycle will invoke the internal refresh
counter for automatic
/
RA
/
S addressing.
?
FUNCTIONAL BLOCK DIAGRAM
FAST PAGE MODE
WE
CAS
DATA-IN
BUFFER
4
NO. 2 CLOCK
GENERATOR
*EARLY WRITE
DETECTION CIRCUIT
DATA-OUT
BUFFER
4
4
DQ1
DQ2
DQ3
DQ4
OE
COLUMN-
ADDRESS
BUFFER(9)
REFRESH
CONTROLLER
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
9
9
COLUMN
DECODER
512
4
SENSE AMPLIFIERS
I/O GATING
512
REFRESH
COUNTER
COMPLEMENT
SELECT
9
ROW-
ADDRESS
BUFFERS (9)
ROW
DECODER
ROW SELECT
(1 of 512)
512
512
9
512
512 x 512 x 4
MEMORY
ARRAY
RAS
NO. 1 CLOCK
GENERATOR
Vcc
Vss
*NOTE:
1. If
?
W
/
E goes LOW prior to
/
C
/
A
/
S going LOW, EW detection circuit output is a HIGH (EARLY WRITE).
2. If
/
C
/
A
/
S goes LOW prior to
?
W
/
E going LOW, EW detection circuit output is a LOW (LATE WRITE).
MT4C4256(L)
REV. 4/94
2
Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
©1994,
Micron Semiconductor, Inc.
OBSOLETE
MT4C4256(L)
256K x 4 DRAM
TRUTH TABLE
ADDRESSES
FUNCTION
Standby
READ
EARLY WRITE
READ WRITE
FAST-PAGE-MODE
READ
FAST-PAGE-MODE
EARLY-WRITE
FAST-PAGE-MODE
READ-WRITE
/
R
?
A
/
S ONLY REFRESH
HIDDEN
REFRESH
CBR REFRESH
Extended Refresh
(MT4C4256 L only)
READ
WRITE
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
?
R
?
A
/
S
H
L
L
L
L
L
L
L
L
L
L
L>H>L
L>H>L
H>L
H>L
?
C
?
A
/
S
H>X
L
L
L
H>L
H>L
H>L
H>L
H>L
H>L
H
L
L
L
L
W
/
E
?
X
H
L
H>L
H
H
L
L
H>L
H>L
X
H
L
X
X
?
O
/
E
X
L
X
L>H
L
L
X
X
L>H
L>H
X
L
X
X
X
t
R
t
C
DATA-IN/OUT
DQ1-DQ4
High-Z
Data-Out
Data-In
Data-Out, Data-In
Data-Out
Data-Out
Data-In
Data-In
Data-Out, Data-In
Data-Out, Data-In
High-Z
Data-Out
Data-In
High-Z
High-Z
X
ROW
ROW
ROW
ROW
n/a
ROW
n/a
ROW
n/a
ROW
ROW
ROW
X
X
X
COL
COL
COL
COL
COL
COL
COL
COL
COL
n/a
COL
COL
X
X
MT4C4256(L)
REV. 4/94
3
Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
©1994,
Micron Semiconductor, Inc.
OBSOLETE
MT4C4256(L)
256K x 4 DRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to V
SS
.................... -1V to +7V
Operating Temperature, T
A
(ambient) .......... 0°C to +70°C
Storage Temperature (plastic) .................... -55°C to +150°C
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... 50mA
*Stresses greater than those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (V
CC
= +5V
±10%)
PARAMETER/CONDITION
Supply Voltage
Input High (Logic 1) Voltage, all inputs
Input Low (Logic 0) Voltage, all inputs
INPUT LEAKAGE CURRENT
Any input 0V
≤
V
IN
≤
6.5V
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT: (Q is disabled; 0V
≤
V
OUT
≤
5.5V)
OUTPUT LEVELS
Output High Voltage (I
OUT
= -5mA)
Output Low Voltage (I
OUT
= 4.2mA)
SYMBOL
V
CC
V
IH
V
IL
I
I
I
OZ
V
OH
V
OL
MIN
4.5
2.4
-1.0
-2
-10
2.4
0.4
MAX
5.5
V
CC
+1
0.8
2
10
UNITS
V
V
V
µA
µA
V
V
NOTES
MAX
PARAMETER/CONDITION
STANDBY CURRENT: (TTL)
(/R
?
A
/
S =
/
C
?
A
/
S = V
IH
)
STANDBY CURRENT: (CMOS)
(/R
?
A
/
S =
/
C
?
A
/
S = V
CC
-0.2V)
OPERATING CURRENT: Random READ/WRITE
Average power supply current
(/R
?
A
/
S,
/
C
?
A
/
S, Single Address Cycling:
t
RC =
t
RC [MIN])
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(/R
?
A
/
S = V
IL
,
/
C
?
A
/
S, Address Cycling:
t
PC =
t
PC [MIN])
REFRESH CURRENT:
/
R
?
A
/
S ONLY
Average power supply current
(/R
?
A
/
S Cycling,
/
C
?
AS = V
IH
:
t
RC =
t
RC [MIN])
/
REFRESH CURRENT: CBR
Average power supply current
(/R
?
A
/
S,
/
C
?
A
/
S, Address Cycling:
t
RC =
t
RC [MIN])
REFRESH CURRENT: Extended
Average power supply current during Extended Refresh:
/
C
?
A
/
S = 0.2V or CBR cycling;
/
R
?
A
/
S =
t
RAS (MIN) to1µs;
W
/
E, A0-A8 and D
IN
= Vcc -0.2V or 0.2V (D
IN
may be
?/
left open);
t
RC = 125µs (512 rows at 125µs = 64ms)
MT4C4256(L)
REV. 4/94
VERSION
SYMBOL
I
CC
1
-6
2
1
200
90
-7
2
-8
2
UNITS
mA
mA
µA
mA
NOTES
MT4C4256
MT4C4256 L
I
CC
2
I
CC
2
I
CC
3
1
1
200 200
80
70
3, 4,
29
3, 4,
29
3, 29
I
CC
4
70
60
50
mA
I
CC
5
90
80
70
mA
I
CC
6
90
80
70
mA
3, 5
MT4C4256 L
I
CC
7
200
200 200
µA
3, 5,
27
4
Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
©1994,
Micron Semiconductor, Inc.
OBSOLETE
MT4C4256(L)
256K x 4 DRAM
CAPACITANCE
PARAMETER
Input Capacitance: A0-A8
Input Capacitance:
/
R
?
A
/
S,
/
C
?
A
/
S,
?
WE,
/
O
/
E
/
Input/Output Capacitance: DQ
SYMBOL
C
I
1
C
I
2
C
IO
MIN
MAX
5
7
7
UNITS
pF
pF
pF
NOTES
2
2
2
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13, 23) (V
CC
= +5V
±10%)
AC CHARACTERISTICS
PARAMETER
Random READ or WRITE cycle time
READ WRITE cycle time
FAST-PAGE-MODE
READ or WRITE cycle time
FAST-PAGE-MODE
READ-WRITE cycle time
-6
SYM
t
RC
t
RWC
t
PC
t
PRWC
-7
MAX
MIN
130
185
40
95
60
20
20
30
35
100,000
100,000
70
20
20
35
40
100,000
100,000
MAX
MIN
150
205
45
100
-8
MAX
UNITS
ns
ns
ns
ns
80
20
20
40
45
100,000
100,000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
15
NOTES
MIN
110
165
35
90
t
RAC
Access time from
/
R
?
A
/
S
t
CAC
Access time from
/
C
?
A
/
S
t
OE
Output Enable
t
AA
Access time from column-address
t
CPA
Access time from
/
C
?
A
/
S precharge
t
RAS
/
R
?
A
/
S pulse width
t
RASP
/
R
?
A
/
S pulse width
(FAST PAGE MODE)
t
RSH
/
R
?
A
/
S hold time
t
RP
/
R
?
A
/
S precharge time
t
CAS
/
C
?
A
/
S pulse width
t
CSH
/
C
?
A
/
S hold time
t
CPN
/
C
?
A
/
S precharge time
/
C
?
A
/
S precharge time
(FAST PAGE MODE)
t
CP
t
RCD
/
R
?
A
/
S to
/
C
?
A
/
S delay time
t
CRP
/
C
?
A
/
S to
/
R
?
A
/
S precharge time
t
ASR
Row-address setup time
t
RAH
Row-address hold time
t
RAD
/
RA
/
S to column-
?
address delay time
60
60
20
40
20
60
10
10
20
5
0
10
15
0
15
45
30
0
0
0
0
100,000
40
30
70
70
20
50
20
70
10
10
20
5
0
10
15
0
15
55
35
0
0
0
0
100,000
50
35
80
80
20
60
20
80
10
10
20
5
0
10
15
0
15
60
40
0
0
0
0
100,000
16
17
60
40
18
Column-address setup time
Column-address hold time
Column-address hold time
(referenced to
/
R
?
A
/
S)
Column-address to
/
RA
/
S lead time
?
Read command setup time
Read command hold time
(referenced to
/
C
?
AS)
/
Read command hold time
(referenced to
/
R
?
AS)
/
/
C
?
A
/
S to output in Low-Z
MT4C4256(L)
REV. 4/94
t
ASC
t
CAH
t
AR
t
RAL
t
RCS
t
RCH
t
RRH
t
CLZ
19
19
5
Micron Semiconductor, Inc., reserves the right to change products or specifications without notice.
©1994,
Micron Semiconductor, Inc.
京公网安备 11010802033920号
EEWORLD
