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MPC9774AE

Description
IC PLL CLK GENERATOR 1:14 52LQFP
Categorylogic    logic   
File Size190KB,12 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
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MPC9774AE Overview

IC PLL CLK GENERATOR 1:14 52LQFP

MPC9774AE Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerNXP
Parts packaging codeQFP
package instructionPLASTIC, LQFP-52
Contacts52
Reach Compliance Codeunknown
Other featuresCAN ALSO OPERATE AT 3.3V SUPPLY
series9774
Input adjustmentMUX
JESD-30 codeS-PQFP-G52
JESD-609 codee0
length10 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Humidity sensitivity level2
Number of functions1
Number of inverted outputs
Number of terminals52
Actual output times14
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)220
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.175 ns
Maximum seat height1.7 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width10 mm
minfmax50 MHz
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9774/D
Rev 2, 05/2003
3.3V 1:14 LVCMOS PLL Clock
Generator
The MPC9774 is a 3.3V compatible, 1:14 PLL based clock generator
targeted for high performance low-skew clock distribution in mid-range to
high-performance networking, computing and telecom applications. With
output frequencies up to 125 MHz and output skews less than 175 ps the
device meets the needs of the most demanding clock applications.
MPC9774
Features
1:14 PLL based low-voltage clock generator
3.3V power supply
Internal power–on reset
Generates clock signals up to 125 MHz
Maximum output skew of 175 ps
Two LVCMOS PLL reference clock inputs
External PLL feedback supports zero-delay capability
Various feedback and output dividers (see application section)
Supports up to three individual generated output clock frequencies
Drives up to 28 clock lines
Ambient temperature range 0°C to +70°C
Pin and function compatible to the MPC974
3.3V 1:14 LVCMOS
PLL CLOCK GENERATOR
FA SUFFIX
52 LEAD LQFP PACKAGE
CASE 848D
Functional Description
The MPC9774 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
MPC9774 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The
reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match
the VCO frequency range.
The MPC9774 features frequency programmability between the three output banks outputs as well as the output to input
relationships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2 and 3:2:1 can be realized. Additionally, the device supports a separate
configurable feedback output which allows for a wide variety of of input/output frequency multiplication alternatives. The
VCO_SEL pin provides an extended PLL input reference frequency range.
The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two
alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL
bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output
dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL
characteristics do not apply.
The MPC9774 has an internal power–on reset.
The MPC9774 is fully 3.3V compatible and requires no external loop filter components. All inputs (except XTAL) accept
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
transmission
lines. For series terminated transmission lines, each of the MPC9774 outputs can drive one or two traces giving the devices an
effective fanout of 1:12. The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP package.
Motorola, Inc. 2003
1

MPC9774AE Related Products

MPC9774AE MPC9774FA
Description IC PLL CLK GENERATOR 1:14 52LQFP IC CLOCK GEN 1:14 PLL LV 52-LQFP
Is it Rohs certified? conform to incompatible
Maker NXP NXP
Parts packaging code QFP QFP
package instruction PLASTIC, LQFP-52 PLASTIC, LQFP-52
Contacts 52 52
Reach Compliance Code unknown not_compliant
Other features CAN ALSO OPERATE AT 3.3V SUPPLY CAN ALSO OPERATE AT 3.3V SUPPLY
series 9774 9774
Input adjustment MUX MUX
JESD-30 code S-PQFP-G52 S-PQFP-G52
JESD-609 code e0 e0
length 10 mm 10 mm
Logic integrated circuit type PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER
Humidity sensitivity level 2 2
Number of functions 1 1
Number of terminals 52 52
Actual output times 14 14
Maximum operating temperature 70 °C 70 °C
Output characteristics 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code LQFP LQFP
Package shape SQUARE SQUARE
Package form FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius) 220 220
Certification status Not Qualified Not Qualified
Same Edge Skew-Max(tskwd) 0.175 ns 0.175 ns
Maximum seat height 1.7 mm 1.7 mm
Maximum supply voltage (Vsup) 3.465 V 3.465 V
Minimum supply voltage (Vsup) 3.135 V 3.135 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V
surface mount YES YES
Temperature level COMMERCIAL COMMERCIAL
Terminal surface TIN LEAD Tin/Lead (Sn/Pb)
Terminal form GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm
Terminal location QUAD QUAD
Maximum time at peak reflow temperature 30 30
width 10 mm 10 mm
minfmax 50 MHz 50 MHz
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