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EPM7128STC100-10F

Description
IC CPLD 128MC 10NS 100TQFP
CategoryProgrammable logic devices    Programmable logic   
File Size2MB,182 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
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EPM7128STC100-10F Overview

IC CPLD 128MC 10NS 100TQFP

EPM7128STC100-10F Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIntel
package instructionLFQFP, TQFP100,.63SQ
Reach Compliance Codecompliant
ECCN codeEAR99
Other featuresYES
maximum clock frequency125 MHz
In-system programmableYES
JESD-30 codeS-PQFP-G100
JESD-609 codee0
JTAG BSTYES
length14 mm
Humidity sensitivity level3
Dedicated input times
Number of I/O lines84
Number of macro cells128
Number of terminals100
Maximum operating temperature70 °C
Minimum operating temperature
organize0 DEDICATED INPUTS, 84 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Encapsulate equivalent codeTQFP100,.63SQ
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)235
power supply3.3/5,5 V
Programmable logic typeEE PLD
propagation delay10 ns
Certification statusNot Qualified
Maximum seat height1.27 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width14 mm
Base Number Matches1
Package Information Datasheet for
Mature Altera Devices
DS-PKG-16.8
This datasheet provides package and thermal resistance information for mature
Altera
®
devices. Package information includes the ordering code reference, package
acronym, leadframe material, lead finish (plating), JEDEC outline reference, lead
coplanarity, weight, moisture sensitivity level, and other special information. The
thermal resistance information includes device pin count, package name, and
resistance values.
This datasheet includes the following sections:
“Device and Package Cross Reference” on page 1
“Thermal Resistance” on page 23
“Package Outlines” on page 44
f
For more package and thermal resistance information about Altera devices that are
not listed in this datasheet, refer to the
Package and Thermal Resistance
page of the
Altera website.
For information about trays, tubes, and dry packs, refer to
AN 71: Guidelines for
Handling J-Lead, QFP, and BGA Devices.
RoHS-compliant devices are compatible with leaded-reflow temperatures. For more
information, refer to
Altera’s RoHS-Compliant Devices
literature page.
f
f
Device and Package Cross Reference
Table 2
through
Table 22
lists the device, package type, and number of pins for each
Altera device listed in this datasheet. Altera devices listed in this datasheet are
available in the following packages:
Ball-Grid Array (BGA)
Ceramic Pin-Grid Array (PGA)
FineLine BGA (FBGA)
Hybrid FineLine BGA (HBGA)
Plastic Dual In-Line Package (PDIP)
Plastic Enhanced Quad Flat Pack (EQFP)
Plastic J-Lead Chip Carrier (PLCC)
Plastic Quad Flat Pack (PQFP)
Power Quad Flat Pack (RQFP)
Thin Quad Flat Pack (TQFP)
Ultra FineLine BGA (UBGA)
© December 2011
Altera Corporation
Package Information Datasheet for Mature Altera Devices

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