Freescale Semiconductor
Technical Data
Document Number: MPC862EC
Rev. 3, 2/2006
MPC862/857T/857DSL
PowerQUICC™ Family
Hardware Specifications
This document contains detailed information on power
considerations, DC/AC electrical characteristics, and AC
timing specifications for the MPC862/857T/857DSL family
(refer to
Table 1
for a list of devices). The MPC862P, which
contains a PowerPC™ core processor, is the superset device
of the MPC862/857T/857DSL family. For functional
characteristics of the processor, refer to the
MPC862
PowerQUICC™ Family Users Manual
(MPC862UM/D).
Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 8
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . 10
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Thermal Calculation and Measurement . . . . . . . . . . 12
Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15
IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 44
CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 46
UTOPIA AC Electrical Specifications . . . . . . . . . . . 68
FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 69
Mechanical Data and Ordering Information . . . . . . . 72
Document Revision History . . . . . . . . . . . . . . . . . . . 86
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© Freescale Semiconductor, Inc., 2006. All rights reserved.
Overview
1
Overview
The MPC862/857T/857DSL is a derivative of Freescale’s MPC860 PowerQUICC™ family of devices. It
is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a
variety of controller applications and communications and networking systems. The
MPC862/857T/857DSL provides enhanced ATM functionality over that of other ATM-enabled members
of the MPC860 family.
Table 1
shows the functionality supported by the members of the MPC862/857T/857DSL family.
Table 1. MPC862 Family Functionality
Cache
Part
Instruction
Cache
16 Kbyte
4 Kbyte
4 Kbyte
4 Kbyte
Data Cache
8 Kbyte
4 Kbyte
4 Kbyte
4 Kbyte
Ethernet
SCC
10T
Up to 4
Up to 4
1
1
10/100
1
1
1
1
4
4
1
1
1
2
2
2
1
2
SMC
MPC862P
MPC862T
MPC857T
MPC857DSL
1
On the MPC857DSL, the SCC (SCC1) is for ethernet only. Also, the MPC857DSL does
not support the Time Slot Assigner (TSA).
2
On the MPC857DSL, the SMC (SMC1) is for UART only.
2
Features
The following list summarizes the key MPC862/857T/857DSL features:
• Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with
thirty-two 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see
Table 1).
– 16-Kbyte instruction cache (MPC862P) is four-way, set-associative with 256 sets; 4-Kbyte
instruction cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative
with 128 sets.
– 8-Kbyte data cache (MPC862P) is two-way, set-associative with 256 sets; 4-Kbyte data
cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative with 128 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks.
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
spaces and 16 protection groups
— Advanced on-chip-emulation debug mode
MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3
2
Freescale Semiconductor
Features
•
•
•
•
•
•
The MPC862/857T/857DSL provides enhanced ATM functionality over that of the MPC860SAR.
The MPC862/857T/857DSL adds major new features available in “enhanced SAR” (ESAR) mode,
including the following:
— Improved operation, administration and maintenance (OAM) support
— OAM performance monitoring (PM) support
— Multiple APC priority levels available to support a range of traffic pace requirements
— ATM port-to-port switching capability without the need for RAM-based microcode
— Simultaneous MII (10/100Base-T) and UTOPIA (half-duplex) capability
— Optional statistical cell counters per PHY
— UTOPIA level 2 compliant interface with added FIFO buffering to reduce the total cell
transmission time. (The earlier UTOPIA level 1 specification is also supported.)
— Multi-PHY support on the MPC857T
— Four PHY support on the MPC857DSL
— Parameter RAM for both SPI and I
2
C can be relocated without RAM-based microcode
— Supports full-duplex UTOPIA both master (ATM side) and slave (PHY side) operation using
a “split” bus
— AAL2/VBR functionality is ROM-resident
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank
— Up to 30 wait states programmable per memory bank
— Glueless interface to Page mode/EDO/SDRAM, SRAM, EPROMs, flash EPROMs, and other
memory devices.
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbyte–256 Mbyte)
— Selectable write protection
— On-chip bus arbitration logic
General-purpose timers
— Four 16-bit timers cascadable to be two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
Fast Ethernet controller (FEC)
— Simultaneous MII (10/100Base-T) and UTOPIA operation when using the UTOPIA
multiplexed bus.
MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3
Freescale Semiconductor
3
Features
•
•
•
•
•
System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Low-power stop mode
— Clock synthesizer
— Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture
— Reset controller
— IEEE 1149.1 test access port (JTAG)
Interrupts
— Seven external interrupt request (IRQ) lines
— 12 port pins with interrupt capability
— The MPC862P and MPC862T have 23 internal interrupt sources; the MPC857T and
MPC857DSL have 20 internal interrupt sources
— Programmable priority between SCCs (MPC862P and MPC862T)
— Programmable highest priority request
Communications processor module (CPM)
— RISC controller
— Communication-specific commands (for example,
GRACEFUL STOP TRANSMIT
,
ENTER HUNT
MODE
, and
RESTART TRANSMIT
)
— Supports continuous mode transmission and reception on all serial channels
— Up to 8-Kbytes of dual-port RAM
— The MPC862P and MPC862T have 16 serial DMA (SDMA) channels; the MPC857T and
MPC857DSL have 10 serial DMA (SDMA) channels
— Three parallel I/O registers with open-drain capability
Four baud rate generators
— Independent (can be connected to any SCC or SMC)
— Allow changes during operation
— Autobaud support option
The MPC862P and MPC862T have four SCCs (serial communication controller) The MPC857T
and MPC857DSL have one SCC, SCC1; the MPC857DSL supports ethernet only
— Serial ATM capability on all SCCs
— Optional UTOPIA port on SCC4
— Ethernet/IEEE 802.3 optional on SCC1–4, supporting full 10-Mbps operation
— HDLC/SDLC
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support PPP (point-to-point protocol)
— AppleTalk
MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3
4
Freescale Semiconductor
Features
•
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•
•
•
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•
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
Two SMCs (serial management channels) (The MPC857DSL has one SMC, SMC1 for UART)
— UART
— Transparent
— General circuit interface (GCI) controller
— Can be connected to the time-division multiplexed (TDM) channels
One serial peripheral interface (SPI)
— Supports master and slave modes
— Supports multiple-master operation on the same bus
One inter-integrated circuit (I
2
C) port
— Supports master and slave modes
— Multiple-master environment support
Time-slot assigner (TSA) (The MPC857DSL does not have the TSA)
— Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame synchronization, clocking
— Allows dynamic changes
— On the MPC862P and MPC862T, can be internally connected to six serial channels (four SCCs
and two SMCs); on the MPC857T, can be connected to three serial channels (one SCC and two
SMCs)
Parallel interface port (PIP)
— Centronics interface support
— Supports fast connection between compatible ports on MPC862/857T/857DSL or MC68360
PCMCIA interface
— Master (socket) interface, release 2.1 compliant
— Supports one or two PCMCIA sockets dependent upon whether ESAR functionality is enabled
— 8 memory or I/O windows supported
Low power support
— Full on—All units fully powered
— Doze—Core functional units disabled except time base decrementer, PLL, memory controller,
RTC, and CPM in low-power standby
MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3
Freescale Semiconductor
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