PCK946
Low voltage 1 : 10 CMOS clock driver
Rev. 01 — 13 December 2005
Product data sheet
1. General description
The PCK946 is a low voltage CMOS 1 : 10 clock buffer. The 10 outputs can be configured
into a standard fan-out buffer or into 1× and
1
⁄
2
×
combinations. The ten outputs were
designed and optimized to drive 50
Ω
series or parallel terminated transmission lines.
With output-to-output skews of 350 ps, the PCK946 is ideal as a clock distribution chip for
synchronous systems which need a tight level of skew from a large number of outputs.
With an output impedance of approximately 7
Ω,
in both the HIGH and LOW logic states,
the output buffers of the PCK946 are ideal for driving series terminated transmission lines.
More specifically, each of the 10 PCK946 outputs can drive two series terminated
transmission lines. With this capability, the PCK946 has an effective fan-out of 1 : 20 in
applications using point-to-point distribution schemes.
The PCK946 has the capability of generating 1× and
1
⁄
2
×
signals from a 1× source. The
design is fully static; the signals are generated and re-timed inside the chip to ensure
minimal skew between the 1× and
1
⁄
2
×
signals. The device features selectability to allow
the user to select the ratio of 1× outputs to
1
⁄
2
×
outputs.
Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can
take advantage of this feature to provide redundant clock sources or the addition of a test
clock into the system design. With the TCLK_SEL input pulled HIGH, the TCLK1 input is
selected.
All of the control inputs are LVCMOS/LVTTL compatible. The DSELn pins choose
between 1× and
1
⁄
2
×
outputs. A LOW on the DSELn pins will select the 1× output. The
MR/OE input will reset the internal flip-flops and 3-state the outputs when it is forced
HIGH.
The PCK946 is fully 3.3 V compatible. The 32-lead LQFP package was chosen to
optimize performance, board space, and cost of the device. The 32-lead LQFP package
has a 7 mm
×
7 mm body size with a conservative 0.8 mm pin spacing.
2. Features
s
s
s
s
s
s
s
2 selectable LVCMOS/LVTTL clock inputs
350 ps output-to-output skew
Drives up to 20 series terminated independent clock lines
Maximum input/output frequency of 150 MHz
3-stateable outputs
32-lead LQFP packaging
3.3 V V
CC
supply voltage
Philips Semiconductors
PCK946
Low voltage 1 : 10 CMOS clock driver
3. Ordering information
Table 1:
Ordering information
Package
Name
PCK946BD
LQFP32
Description
plastic low profile quad flat package; 32 leads;
body 7
×
7
×
1.4 mm
Version
SOT358-1
Type number
4. Functional diagram
TCLK_SEL
TCLK0
(internal pull-down)
(internal pull-up)
÷
1
÷
2
1
R
PCK946
0
3
0
TCLK1
(internal pull-up)
QA[0:2]
1
DSELA
(internal pull-down)
0
3
QB[0:2]
1
DSELB
(internal pull-down)
0
4
QC[0:3]
1
DSELC
MR/OE
(internal pull-down)
(internal pull-down)
002aaa676
Fig 1. Functional diagram of PCK946
9397 750 12296
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 13 December 2005
2 of 13
Philips Semiconductors
PCK946
Low voltage 1 : 10 CMOS clock driver
5. Pinning information
5.1 Pinning
32 MR/OE
31 GND
27 GND
30 QA0
26 QA2
28 QA1
29 V
CC
TCLK_SEL
VCCI
TCLK0
TCLK1
DSELA
DSELB
DSELC
GNDI
1
2
3
4
5
6
7
8
QC0 10
GND 11
QC1 12
V
CC
13
QC2 14
GND 15
QC3 16
9
25 V
CC
24 GND
23 QB0
22 V
CC
21 QB1
20 GND
19 QB2
18 V
CC
17 V
CC
002aaa677
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
PCK946BD
Fig 2. Pin configuration for LQFP32
5.2 Pin description
Table 2:
Symbol
DSELA, DSELB, DSELC
GND
GNDI
MR/OE
QA0, QA1, QA2
QB0, QB1, QB2
QC0, QC1, QC2, QC3
TCLK_SEL
TCLK0, TCLK1
V
CC
VCCI
Pin description
Pin
5, 6, 7
11, 15, 20, 24,
27, 31
8
32
30, 28, 26
23, 21, 19
10, 12, 14, 16
1
3, 4
9, 13, 17, 18,
22, 25, 29
2
Description
output bank divide select input
ground
ground
internal reset and output (high-impedance) control
bank A outputs
bank B outputs
bank C outputs
CMOS clock select input
CMOS clock inputs
supply voltage
supply voltage
9397 750 12296
Product data sheet
Rev. 01 — 13 December 2005
V
CC
3 of 13
Philips Semiconductors
PCK946
Low voltage 1 : 10 CMOS clock driver
6. Functional description
6.1 Function table
Table 3:
0
1
Table 4:
DSELn
0
1
Table 5:
MR/OE
0
1
TCLK_SEL function table
Input
TCLK0
TCLK1
DSELn function table
Outputs
1×
1
⁄ ×
2
TCLK_SEL
MR/OE function table
Outputs
enabled
high-impedance
7. Limiting values
Table 6:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC
V
I
I
I
T
stg
Parameter
supply voltage
input voltage
input current
storage temperature
CMOS inputs
Conditions
Min
−0.3
−0.3
-
−40
Max
+4.6
V
CC
+ 0.3
±20
+125
Unit
V
V
mA
°C
9397 750 12296
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 13 December 2005
4 of 13
Philips Semiconductors
PCK946
Low voltage 1 : 10 CMOS clock driver
8. Static characteristics
Table 7:
Static characteristics
T
amb
= 0
°
C to +70
°
C; V
CC
= 3.3 V
±
0.3 V
Symbol
V
IH
V
IL
V
OH
V
OL
I
I
C
i
C
PD
I
q(max)
[1]
[2]
Parameter
HIGH-state input voltage
LOW-state input voltage
HIGH-state output voltage
LOW-state output voltage
input current
input capacitance
power dissipation capacitance
maximum quiescent supply current
Conditions
Min
2.0
-
Typ
-
-
-
-
-
-
25
1
Max
3.6
0.8
-
0.4
±120
4
-
2
Unit
V
V
V
V
µA
pF
pF
mA
I
OH
=
−20
mA
I
OL
= 20 mA
[1]
[1]
[2]
2.5
-
-
-
-
-
per output
The PCK946 can drive 50
Ω
transmission lines on the incident edge. Each output can drive one 50
Ω
parallel terminated transmission
line to the termination voltage of V
T
= 0.5V
CC
. Alternately, the device drives up to two 50
Ω
series terminated transmission lines.
I
I
current is a result of internal pull-up/pull-down resistors.
9. Dynamic characteristics
Table 8:
Symbol
f
max
t
PLH
t
PHL
t
sk(o)
Dynamic characteristics
Parameter
maximum input clock frequency
LOW-to-HIGH propagation delay
HIGH-to-LOW propagation delay
output skew time
TCLK to Qn
TCLK to Qn
output-to-output
f
max
< 100 MHz;
same frequency outputs
f
max
< 100 MHz;
different frequency outputs
f
max
> 100 MHz;
same frequency outputs
f
max
> 100 MHz;
different frequency outputs
t
sk(pr)
t
PZL
t
PZH
t
PLZ
t
PHZ
t
r
t
f
[1]
[2]
[3]
Conditions
[1]
[1] [2]
[1] [2]
[1] [2]
Min
150
4.5
4.5
-
-
-
-
[3]
[2]
[2]
[2]
[2]
Typ
-
7.5
7.5
-
-
-
-
2.0
3
3
3
3
0.5
0.5
Max
-
11.5
11.5
350
350
350
450
4.5
11
11
11
11
1.0
1.0
Unit
MHz
ns
ns
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
process skew time
OFF-state to LOW propagation delay
OFF-state to HIGH propagation delay
LOW to OFF-state propagation delay
HIGH to OFF-state propagation delay
rise time
fall time
part-to-part
-
-
-
-
-
0.1
0.1
output; 0.8 V to 2.0 V
output; 2.0 V to 0.8 V
[2]
[2]
Driving 50
Ω
transmission lines.
Termination is 50
Ω
to 0.5V
CC
.
Part-to-part skew at a given temperature and voltage.
9397 750 12296
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 13 December 2005
5 of 13
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