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Advance Information
MPC8240EC
Rev. 4, 11/2003
MPC8240
Integrated Processor
Hardware Specifications
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The MPC8240 combines a MPC603e core microprocessor with a PCI bridge. The MPC8240
PCI support allows system designers to rapidly create systems using peripherals already
designed for PCI and the other standard interfaces. The MPC8240 also integrates a
high-performance memory controller that supports various types of DRAM and ROM. The
MPC8240 is the first of a family of products that provide system-level support for industry
standard interfaces with PowerPC™ microprocessor cores.
This hardware specification describes pertinent electrical and physical characteristics of the
MPC8240. For functional characteristics of the processor, refer to the
MPC8240 Integrated
Processor User’s Manual
(MPC8240UM).
This hardware specification contains the following topics:
Topic
Section 1.1, “Overview”
Section 1.2, “Features”
Section 1.3, “General Parameters”
Section 1.4, “Electrical and Thermal Characteristics”
Section 1.5, “Package Description”
Section 1.6, “PLL Configurations”
Section 1.7, “System Design Information”
Section 1.8, “Document Revision History”
Section 1.9, “Ordering Information”
Page
1
3
5
5
27
34
35
45
49
To locate any published errata or updates for this document, refer to the website at
http://www.motorola.com/semiconductors.
1.1
Overview
The MPC8240 integrated processor is comprised of a peripheral logic block and a 32-bit
superscalar MPC603e core, as shown in Figure 1.
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Overview
MPC8240
Additional Features:
• Prog I/O with Watchpoint
• JTAG/COP Interface
• Power Management
Processor Core Block
Processor
PLL
(64-Bit) Two-Instruction Fetch
Branch
Processing
Instruction Unit
Unit
(BPU)
(64-Bit) Two-Instruction Dispatch
System
Register
Unit
(SRU)
Integer
Unit
(IU)
Load/Store
Unit
(LSU)
Floating-
Point
Unit
(FPU)
64-Bit
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Data
MMU
16-Kbyte
Data
Cache
Instruction
MMU
16-Kbyte
Instruction
Cache
Peripheral Logic Bus
Peripheral Logic Block
Message
Unit
(with I
2
O)
Address
(32-Bit)
Data (64-Bit)
Data Path
ECC Controller
Data Bus
(32- or 64-Bit)
with 8-Bit Parity
or ECC
Address/Control
DRAM/SDRAM/
ROM/Flash/Port X
SDRAM Sync In
DMA
Controller
Central
Control
Unit
Configuration
Registers
Memory
Controller
I
2
C
I
2
C
Controller
PIC
Interrupt
Controller/
Timers
DLL
PCI Bus
Interface Unit
Address
Translator
PCI
Arbiter
SDRAM Sync Out
SDRAM Clocks
PCI Clock In
PCI Bus Clocks
5 IRQs/
16 Serial
Interrupts
Peripheral Logic
PLL
Fanout
Buffers
32-Bit
Five
PCI Interface Request/Grant
Pairs
OSC In
Figure 1. MPC8240 Block Diagram
The peripheral logic integrates a PCI bridge, memory controller, DMA controller, PIC interrupt controller,
I
2
O controller, and an I
2
C controller. The MPC603e core is a full-featured, high-performance processor with
floating-point support, memory management, a 16-Kbyte instruction cache, a 16-Kbyte data cache, and
2
MPC8240 Integrated Processor Hardware Specifications
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Features
power management features. The integration reduces the overall packaging requirements and the number of
discrete devices required for an embedded system.
The MPC8240 contains an internal peripheral logic bus that interfaces the MPC603e core to the peripheral
logic. The core can operate at a variety of frequencies, allowing the designer to trade off performance for
power consumption. The MPC603e core is clocked from a separate PLL, which is referenced to the
peripheral logic PLL. This allows the microprocessor and the peripheral logic block to operate at different
frequencies while maintaining a synchronous bus interface. The interface uses a 64- or 32-bit data bus
(depending on memory data bus width) and a 32-bit address bus along with control signals that enable the
interface between the processor and peripheral logic to be optimized for performance. PCI accesses to the
MPC8240 memory space are passed to the processor bus for snooping purposes when snoop mode is
enabled.
The MPC8240 features serve a variety of embedded applications. In this way, the MPC603e core and
peripheral logic remain general-purpose. The MPC8240 can be used as either a PCI host or an agent
controller.
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1.2
•
Features
Peripheral logic
— Memory interface
– Programmable timing supporting either FPM DRAM, EDO DRAM, or SDRAM
– High-bandwidth bus (32- or 64-bit data bus) to DRAM
– Supports one to eight banks of 4-, 16-, 64-, or 128-Mbit memory devices
– Supports 1-Mbyte to 1-Gbyte DRAM memory
– 16 Mbytes of ROM space
– 8-, 32-, or 64-bit ROM
– Write buffering for PCI and processor accesses
– Supports normal parity, read-modify-write (RMW), or ECC
– Data-path buffering between memory interface and processor
– Low-voltage TTL logic (LVTTL) interfaces
– Port X: 8-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with
programmable address strobe timing
— 32-bit PCI interface operating up to 66 MHz
– PCI 2.1-compliant
– PCI 5.0-V tolerance
– Support for PCI locked accesses to memory
– Support for accesses to PCI memory, I/O, and configuration spaces
– Selectable big- or little-endian operation
– Store gathering of processor-to-PCI write and PCI-to-memory write accesses
– Memory prefetching of PCI read accesses
– Selectable hardware-enforced coherency
– PCI bus arbitration unit (five request/grant pairs)
– PCI agent mode capability
MPC8240 Integrated Processor Hardware Specifications
3
This section summarizes features of the MPC8240. Major features of the MPC8240 are as follows:
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Features
•
•
•
•
– Address translation unit
– Some internal configuration registers accessible from PCI
— Two-channel integrated DMA controller (writes to ROM/Port X not supported)
– Supports direct mode or chaining mode (automatic linking of DMA transfers)
– Supports scatter gathering—Read or write discontinuous memory
– Interrupt on completed segment, chain, and error
– Local-to-local memory
– PCI-to-PCI memory
– PCI-to-local memory
– PCI memory-to-local memory
— Message unit
– Two doorbell registers
– Two inbound and two outbound messaging registers
– I
2
O message controller
— I
2
C controller with full master/slave support (except broadcast all)
— Programmable interrupt controller (PIC)
– Five hardware interrupts (IRQs) or 16 serial interrupts
– Four programmable timers
— Integrated PCI bus, CPU, and SDRAM clock generation
— Programmable PCI bus, 60x, and memory interface output drivers
Dynamic power management—Supports 60x nap, doze, and sleep modes
Programmable input and output signals with watchpoint capability
Built-in PCI bus performance monitor facility
— Debug features
– Memory attribute and PCI attribute signals
– Debug address signals
– MIV signal—Marks valid address and data bus cycles on the memory bus
– Error injection/capture on data path
– IEEE 1149.1 (JTAG)/test interface
Processor core interface
— High-performance, superscalar processor core
— Integer unit (IU), floating-point unit (FPU) (software enabled or disabled), load/store unit
(LSU), system register unit (SRU), and a branch processing unit (BPU)
— 16-Kbyte instruction cache
— 16-Kbyte data cache
— Lockable L1 cache, entire cache or on a per-way basis
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General Parameters
1.3
General Parameters
Technology
Die size
Transistor count
Logic design
Packages
Core power supply
I/O power supply
0.29-µm CMOS, five-layer metal
73 mm
2
3.1 million
Fully-static
Surface mount 352 tape ball grid array (TBGA)
2.5 V ± 5% V DC (nominal; see Table 2 for recommended operating
conditions)
3.0- to 3.6-V DC
The following list provides a summary of the general parameters of the MPC8240:
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1.4
1.4.1
Electrical and Thermal Characteristics
DC Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8240.
The following sections describe the MPC8240 absolute maximum ratings, recommended operating
conditions, DC electrical specifications, output driver characteristics, and power data characteristics.
1.4.1.1
Absolute Maximum Ratings
The tables in this section describe the MPC8240 DC electrical characteristics. Table 1 provides the absolute
maximum ratings.
Table 1. Absolute Maximum Ratings
Characteristic
1
Supply voltage—CPU core and peripheral logic
Supply voltage—memory bus drivers
Supply voltage—PCI and standard I/O buffers
Supply voltage—PLLs and DLL
Supply voltage—PCI reference
Input voltage
2
Operational die-junction temperature range
Storage temperature range
Symbol
V
DD
GV
DD
OV
DD
AV
DD
/AV
DD
2/LAV
DD
LVD
DD
V
in
T
j
T
stg
Range
–0.3 to 2.75
–0.3 to 3.6
–0.3 to 3.6
–0.3 to 2.75
–0.3 to 5.4
–0.3 to 3.6
0 to 105
–55 to 150
Unit
V
V
V
V
V
V
°C
°C
Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only,
and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device
reliability or cause permanent damage to the device.
2. PCI inputs with LV
DD
= 5 V ± 5% V DC may be correspondingly stressed at voltages exceeding LV
DD
+ 0.5 V DC.
MPC8240 Integrated Processor Hardware Specifications
5
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