74HCT299N,652 datasheet, PDF - EEWORLD Datasheet

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74HCT299N,652: DescriptionIC UNIV SHIFT REGISTER 20DIP; Categorylogic logic; File Size144KB，24 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74HCT299N,652 Overview

IC UNIV SHIFT REGISTER 20DIP

74HCT299N,652 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	DIP
package instruction	DIP, DIP20,.3
Contacts	20
Reach Compliance Code	compliant
Other features	HOLD MODE; COMMON I/O PINS; TOTEMPOLE SERIAL SHIFT RIGHT & SHIFT LEFT OUTPUTS; GATED OUTPUT CONTROL
Counting direction	BIDIRECTIONAL
series	HCT
JESD-30 code	R-PDIP-T20
JESD-609 code	e4
length	26.73 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	PARALLEL IN PARALLEL OUT
Maximum Frequency@Nom-Sup	20000000 Hz
Number of digits	8
Number of functions	1
Number of terminals	20
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP20,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	260
power supply	5 V
propagation delay (tpd)	56 ns
Certification status	Not Qualified
Maximum seat height	4.2 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Trigger type	POSITIVE EDGE
width	7.62 mm
minfmax	17 MHz
Base Number Matches	1

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74HC299; 74HCT299

8-bit universal shift register; 3-state

Rev. 03 — 28 July 2008

Product data sheet

1. General description

The 74HC299; 74HCT299 are high-speed Si-gate CMOS devices which are

pin-compatible with Low-power Schottky TTL (LSTTL) devices. They are speciﬁed in

compliance with JEDEC standard no. 7A.

The 74HC299; 74HCT299 contain eight edge-triggered D-type ﬂip-ﬂops and the

interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and

hold operations. An operation is determined by the mode select inputs S0 and S1, as

shown in

Table 3.

Pins I/O0 to I/O7 are ﬂip-ﬂop 3-state buffer outputs which allow them to operate as data

inputs in parallel load mode. The serial outputs Q0 and Q7 are used for expansion in

serial shifting of longer words.

A LOW signal on the asynchronous master reset input MR overrides the Sn and clock CP

inputs and resets the ﬂip-ﬂops. All other state changes are initiated by the rising edge of

the clock pulse. Inputs can change when the clock is in either state, provided that the

recommended set-up and hold times are observed.

A HIGH signal on the 3-state output enable inputs OE1 or OE2 disables the 3-state

buffers and the I/On outputs are set to the high-impedance OFF-state. In this condition,

the shift, hold, load and reset operations still occur when preparing for a parallel load

operation. The 3-state buffers are also disabled by HIGH signals on both S0 and S1.

2. Features

Multiplexed inputs/outputs provide improved bit density

Four operating modes:

Shift left

Shift right

Hold (store)

Load data

Operates with output enable or at high-impedance OFF-state (Z)

3-state outputs drive bus lines directly

Cascadable for n-bit word lengths

ESD protection:

HBM JESD22-A114E exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

Speciﬁed from

−40 °C

to +85

°C

and from

−40 °C

to +125

°C

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Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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