MT9V024/D
1/3-Inch Wide VGA CMOS
Digital Image Sensor
Description
The MT9V024 is a 1/3−inch wide−VGA format CMOS active−pixel
digital image sensor with global shutter and high dynamic range
(HDR) operation. The sensor has specifically been designed to support
the demanding interior and exterior automotive imaging needs, which
makes this part ideal for a wide variety of imaging applications in
real−world environments.
Table 1. KEY PERFORMANCE PARAMETERS
Parameter
Optical Format
Active Imager Size
Active Pixels
Pixel Size
Color Filter Array
Shutter Type
Maximum Data Rate
Master Clock
Full Resolution
Frame Rate
ADC Resolution
Responsivity
Dynamic Range
Supply Voltage
Power Consumption
1/3-inch
4.51 mm (H)
×
2.88 mm (V)
5.35 mm Diagonal
752 H
×
480 V
6.0
mm
×
6.0
mm
Monochrome or Color RGB Bayer or RCCC Pattern
Global Shutter
27 Mp/s
27 MHz
752
×
480
60 fps (at Full Resolution)
10−bit Column−Parallel
4.8 V/lux−sec (550 nm)
> 55 dB Linear;
> 100 dB in HDR Mode
3.3 V
±
0.3 V (All Supplies)
< 160 mW at Maximum Data Rate (LVDS
Disabled);
120
mW
Standby Power at 3
−40°C
to + 105°C
52−ball iBGA, Automotive−qualified; Wafer or Die
Value
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IBGA52
CASE 503AA
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Features
(continued)
•
Window Size: User Programmable to Any
•
•
•
Operating Tempera-
ture
Packaging
Features
•
•
•
Array Format: Wide−VGA, Active 752 H x 480 V
•
•
•
•
•
•
•
(360,960 pixels)
Global Shutter Photodiode Pixels; Simultaneous Integration and
Readout
RGB Bayer, Monochrome, or RCCC: NIR Enhanced Performance
for Use with Non−visible NIR Illumination
Readout Modes: Progressive or Interlaced
Shutter Efficiency: >99%
Simple Two−Wire Serial Interface
Real−Time Exposure Context Switching−Dual Register Set
Register Lock Capability
•
Smaller Format (QVGA, CIF, QCIF). Data
Rate Can Be Maintained Independent of
Window Size
Binning: 2 x 2 and 4 x 4 of The Full Resolu-
tion
ADC: On−Chip, 10−bit Column−Parallel
(Option to Operate in 12−bit to 10−bit
Companding Mode)
Automatic Controls: Auto Exposure Control
(AEC) and Auto Gain Control (AGC); Vari-
able Regional and Variable Weight AEC/
AGC
Support for Four Unique Serial Control
Register IDs to Control Multiple Imagers on
the Same Bus
Data Output Formats:
♦
Single Sensor Mode:
10−bit Parallel/Stand−Alone
8−bit or 10−bit Serial LVDS
♦
Stereo Sensor Mode: Interspersed 8−bit
Serial LVDS
High Dynamic Range (HDR) Mode
©
Semiconductor Components Industries, LLC, 2006
December, 2017
−
Rev. 7
1
Publication Order Number:
MT9V024/D
MT9V024/D
Applications
•
Automotive
•
Unattended Surveillance
•
Stereo Vision
ORDERING INFORMATION
Table 2. AVAILABLE PART NUMBERS
Part Number
MT9V024D00XTCC13CC1−200
MT9V024D00XTMC13CC1−200
MT9V024D00XTRC13CC1-200
MT9V024D00XTRC13CC1-400
MT9V024IA7XTC-DP
MT9V024IA7XTC-DR
MT9V024IA7XTM-DP
MT9V024IA7XTM-DR
MT9V024IA7XTM-TP
MT9V024IA7XTM-TR
MT9V024IA7XTR-DP
MT9V024IA7XTR-DR
MT9V024IA7XTR-TP
MT9V024IA7XTR-TR
Product Description
VGA 1/3” GS CIS
VGA 1/3” GS CIS
VGA 1/3” GS CIS
VGA 1/3” GS CIS
VGA 1/3” GS CIS
VGA 1/3” GS CIS
VGA 1/3” GS CIS
VGA 1/3” GS CIS
WVGA 1/3” GS CIS
WVGA 1/3” GS CIS
VGA 1/3” GS CIS
VGA 1/3” GS CIS
VGA 1/3” GS CIS
VGA 1/3” GS CIS
•
•
•
•
Smart vision
Automation
Video as input
Machine vision
Orderable Product Attribute Description
Die Sales, 200mm Thickness
Die Sales, 200mm Thickness
Die Sales, 200mm Thickness
Die Sales, 400mm Thickness
Dry Pack with Protective Film
Dry Pack without Protective Film
Dry Pack with Protective Film
Dry Pack without Protective Film
Tape & Reel with Protective Film
Tape & Reel without Protective Film
Dry Pack with Protective Film
Dry Pack without Protective Film
Tape & Reel with Protective Film
Tape & Reel without Protective Film
GENERAL DESCRIPTION
The MT9V024 is a 1/3−inch wide−VGA format CMOS
active−pixel digital image sensor with global shutter and
high dynamic range (HDR) operation. The sensor has
specifically been designed to support the demanding interior
and exterior automotive imaging needs, which makes this
part ideal for a wide variety of imaging applications in
real−world environments.
This wide−VGA CMOS image sensor features ON
Semiconductor’s breakthrough low−noise CMOS imaging
technology that achieves CCD image quality (based on
signal−to−noise ratio and low−light sensitivity) while
maintaining the inherent size, cost, and integration
advantages of CMOS.
The active imaging pixel array is 752H x 480V. It
incorporates sophisticated camera functions on−chip−such
as binning 2 x 2 and 4 x 4, to improve sensitivity when
operating in smaller resolutions−as well as windowing,
column and row mirroring. It is programmable through
a simple two−wire serial interface.
The MT9V024 can be operated in its default mode or be
programmed for frame size, exposure, gain setting, and
other parameters. The default mode outputs
a wide−VGA−size image at 60 frames per second (fps).
An on−chip analog−to−digital converter (ADC) provides
10 bits per pixel. A 12−bit resolution companded for 10 bits
for small signals can be alternatively enabled, allowing more
accurate digitization for darker areas in the image.
In addition to a traditional, parallel logic output the
MT9V024 also features a serial low−voltage differential
signaling (LVDS) output. The sensor can be operated in
a stereo−camera, and the sensor, designated as
a stereo−master, is able to merge the data from itself and the
stereo−slave sensor into one serial LVDS stream.
The sensor is designed to operate in a wide temperature
range (–40_C to + 105_C).
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2
MT9V024/D
Control Register
Active−Pixel
Sensor (APS)
Array
752 H x 480 V
Serial
Register
I/O
Timing and Control
Analog
Processing
ADCs
Digital Processing
Parallel
Video
Data Out
Slave Video LVDS In
(for stereo applications only)
Serial Video
LVDS Out
Figure 1. Block Diagram
1
V
DD
LVDS
2
SER
DATA
OUT P
SHFT
CLKOUT
P
BYPASS
_CLKIN
_N
SER
DATIN
_N
3
SER
DATA
OUT N
SHFT_
CLKOUT
N
4
V
DD
LVDS
5
SYS−
CLK
6
D
OUT
0
7
D
OUT
2
8
D
OUT
3
A
B
LVDS
GND
V
DD
PIXCLK
D
OUT
1
D
OUT
4
VAAPIX
C
BYPASS
_CLKIN
_P
SER
DATA IN
_P
LVDS
GND
D
GND
A
GND
V
AA
D
NC
NC
E
D
OUT
5
V
DD
NC
NC
F
D
OUT
6
D
OUT
7
D
GND
A
GND
V
AA
STAND−
BY
G
D
OUT
8
FRAME_
VALID
STLN_
OUT
S
DATA
STFRM_
OUT
LED_
OUT
S_CTRL
_ADR0
RESET_
BAR
H
D
OUT
9
LINE_
VALID
EXPO−
SURE
SCLK
ERROR
OE
RSVD
S_CTRL
_ADR1
Figure 2. Top View (Ball Down)
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MT9V024/D
BALL DESCRIPTIONS
Table 3. BALL DESCRIPTIONS
52−Ball IBA
Numbers
H7
D2
D1
C2
C1
H3
H4
H6
G7
H8
G8
F8
A5
G4
G3
G5
H2
G2
E1
F1
F2
G1
H1
H5
G6
B7
A8
A7
B6
A6
B5
B3
B2
Symbol
RSVD
SER_DATAIN_N
SER_DATAIN_P
BYPASS_CLKIN_N
BYPASS_CLKIN_P
EXPOSURE
SCLK
OE
S_CTRL_ADR0
S_CTRL_ADR1
RESET_BAR
STANDBY
SYSCLK
S
DATA
STLN_OUT
STFRM_OUT
LINE_VALID
FRAME_VALID
D
OUT
5
D
OUT
6
D
OUT
7
D
OUT
8
D
OUT
9
ERROR
LED_OUT
D
OUT
4
D
OUT
3
D
OUT
2
D
OUT
1
D
OUT
0
PIXCLK
SHFT_CLKOUT_N
SHFT_CLKOUT_P
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Connect to D
GND
Serial data in for stereoscopy (differential negative). Tie to 1 kW pull−up (to 3.3 V)
in non−stereoscopy mode
Serial data in for stereoscopy (differential positive). Tie to D
GND
in
non−stereoscopy mode
Input bypass shift−CLK (differential negative). Tie to 1 kW pull−up
(to 3.3 V) in non−stereoscopy mode
Input bypass shift−CLK (differential positive). Tie to D
GND
in
non−stereoscopy mode
Rising edge starts exposure in snapshot and slave modes
Two−wire serial interface clock. Connect to V
DD
with 1.5 kW resistor even when no
other two−wire serial interface peripheral is attached
D
OUT
enable pad, active HIGH
Two−wire serial interface slave address select (see Table 4 on page 12)
Two−wire serial interface slave address select (see Table 4 on page 12)
Asynchronous reset. All registers assume defaults
Shut down sensor operation for power saving
Master clock (26.6 MHz; 13 MHz – 27 MHz)
Two−wire serial interface data. Connect to V
DD
with 1.5 kW resistor even when no
other two−wire serial interface peripheral is attached
Output in master mode−start line sync to drive slave chip in−phase; input in slave
mode
Output in master mode−start frame sync to drive a slave chip in−phase; input in
slave mode
Asserted when D
OUT
data is valid
Asserted when D
OUT
data is valid
Parallel pixel data output 5
Parallel pixel data output 6
Parallel pixel data output 7
Parallel pixel data output 8
Parallel pixel data output 9
Error detected. Directly connected to STEREO ERROR FLAG
LED strobe output
Parallel pixel data output 4
Parallel pixel data output 3
Parallel pixel data output 2
Parallel pixel data output 1
Parallel pixel data output 0
Pixel clock out. D
OUT
is valid on rising edge of this clock
Output shift CLK (differential negative)
Output shift CLK (differential positive)
Descriptions
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4
MT9V024/D
52−Ball IBA
Numbers
A3
A2
B4, E2
C8, F7
B8
A1, A4
B1, C3
C6, F3
C7, F6
E7, E8, D7, D8
Symbol
SER_DATAOUT_N
SER_DATAOUT_P
V
DD
V
AA
VAAPIX
V
DD
LVDS
LVDSGND
D
GND
A
GND
NC
Type
Output
Output
Supply
Supply
Supply
Supply
Ground
Ground
Ground
NC
Descriptions
Serial data out (differential negative)
Serial data out (differential positive)
Digital power 3.3 V
Analog power 3.3 V
Pixel power 3.3 V
Dedicated power for LVDS pads
Dedicated GND for LVDS pads
Digital GND
Analog GND
No connect (Note 3)
1. Pin H7 (RSVD) must be tied to GND.
2. Output enable (OE) tri−states signals D
OUT
0−D
OUT
9, LINE_VALID, FRAME_VALID, and PIXCLK.
3. No connect. These pins must be left floating for proper operation.
V
DD
10KW
1.5KW
Master Clock
STANDBY from
Controller or
Digital GND
Two−Wire
Serial Interface
0.1mF
NOTE:
V
DD
LVDS
V
DD
V
AA
V
AA
VAAPIX
VAAPIX
D
OUT
(9:0)
LINE_VALID
FRAME_VALID
PIXCLK
LED_OUT
ERROR
SYSCLK
OE
RESET_BAR
EXPOSURE
STANDBY
S_CTRL_ADR0
S_CTRL_ADR1
SCLK
SDATA
To Controller
To LED Output
RSVD
D
GND
LVDSGND
A
GND
LVDS signals are to be left floating.
Figure 3. Typical Configuration (Connection)−Parallel Output Mode
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