P4080NSN7MMC datasheet, PDF - EEWORLD Datasheet

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P4080NSN7MMC: DescriptionMPU QorIQ P4080 RISC 32bit 45nm 1.2GHz 1.5V/1.8V/2.5V/3.3V 1295-Pin FCBGA Tray; File Size316KB，3 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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P4080NSN7MMC Overview

MPU QorIQ P4080 RISC 32bit 45nm 1.2GHz 1.5V/1.8V/2.5V/3.3V 1295-Pin FCBGA Tray

P4080NSN7MMC Parametric

Parameter Name	Attribute value
EU restricts the use of certain hazardous substances	Compliant
ECCN (US)	3A991A1
Part Status	LTB
HTS	8542.31.00.01
Family Name	QorIQ P4080
Instruction Set Architecture	RISC
Device Core	e500mc
Core Architecture	e500
Number of CPU Cores	8
Data Bus Width (bit)	32
Instruction Cache Size	32KB
Maximum Speed (MHz)	1200
Interface Type	Ethernet/I2C/SPI/UART/USB
UART	2
USART	0
Data Cache Size	32KB
USB	1
Multiply Accumulate	No
SPI	1
I2C	2
I2S	0
CAN	0
Memory Card Interface	MMC/SD
Ethernet	10
Ethernet Interface Type	SGMII
Ethernet Speed	10Mbps/100Mbps/1000Mbps
Minimum Operating Supply Voltage (V)	0.95
Typical Operating Supply Voltage (V)	1
Maximum Operating Supply Voltage (V)	1.05
I/O Voltage (V)	1.8\|1.5\|2.5\|3.3
Minimum Operating Temperature (°C)	0
Maximum Operating Temperature (°C)	125
Packaging	Tray
Supplier Package	FCBGA
Pin Count	1295
Standard Package Name	BGA
Mounting	Surface Mount
Package Height	2.94(Max)
Package Length	37.5
Package Width	37.5
PCB changed	1295
Lead Shape	Ball

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Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t

he Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony

are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack,

ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ

Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks

of Freescale Semiconductor, Inc. All other product or service names are the property

Title:

Duplicate edge-triggered interrupt after priority re-arbitration.

Description:

There is an occurrence of duplicate interrupt when an edge-triggered interrupt higher in priority comes closely to any other enabled interrupts. The following

is the sequence of events that leads to the duplicate edge-triggered interrupt::

•

1. An active interrupt is waiting for acknowledgement

2. An edge-triggered interrupt of higher priority triggers closely to the lower priority interrupt just when it is acknowledged

3. The higher priority edge-triggered interrupt supersedes and fires a new interrupt to the core

4. The core acknowledges the higher priority interrupt without clearing the pending state and finishes the interrupt service routine with EOI

5. A duplicate of the higher priority edge-triggered interrupt is triggered because of the uncleared pending state

Impact:

Enabling any edge-triggered interrupts higher in priority than other enabled interrupts may lead to the duplicate edge-triggered interrupt. This includes

edge-triggered IRQs, global timers and IPI.

Workaround:

Chose one of the following workarounds based on the interrupt type:

• Configure the higher priority interrupts as level-sensitive only

a. In case of IRQs this can be configured in the Vector/Priority Register.

b. It is not an option for global timers or IPI.

• Any enabled edge-triggered interrupts must be no higher in priority than the other enabled interrupts.

Resolution:

No plan to fix

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore

and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a

Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc.

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