530GB124M520DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 530GB124M520DG

530GB124M520DG: DescriptionSINGLE FREQUENCY XO, OE PIN 2 (O; CategoryPassive components oscillator; File Size450KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530GB124M520DG Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	530GB124M520DG	-	-	View	Buy Now

530GB124M520DG Overview

SINGLE FREQUENCY XO, OE PIN 2 (O

530GB124M520DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
package instruction	DILCC6,.2
Reach Compliance Code	compliant
JESD-609 code	e3
Installation features	SURFACE MOUNT
Number of terminals	6
Maximum operating frequency	160 MHz
Minimum operating frequency	10 MHz
Nominal operating frequency	124.52 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output low current	32 mA
Package body material	PLASTIC/EPOXY
Encapsulate equivalent code	DILCC6,.2
power supply	2.5 V
Certification status	Not Qualified
Maximum slew rate	88 mA
Nominal supply voltage	2.5 V
surface mount	YES
Terminal surface	Matte Tin (Sn)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R YS TA L

SCILLATOR

(XO) (10 M H

Features

Available with any-rate output



frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz



3rd generation DSPLL

with superior



jitter performance



3x better frequency stability than



SAW-based oscillators



1.4 GH

)

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout



Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH



Networking



SD/HD video



Test and measurement



Clock and data recovery



FPGA/ASIC clock generation



Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.5 6/18

Si530/531

Recommended Resources

Drawer alarm circuit that “recognizes people”

HA17385 switching power supply integrated controller internal equivalent circuit diagram

Neutral line break protection circuit

High current thyristor pulse power supply circuit

30kHz bandwidth isolation circuit

Massager circuit diagram SCH

Big-eyed girl with slender thighs and thin gauze clothes as thin as cicada clothes still hugs the steel pipe and half covers her face (with pictures as evidence): ...; 探路者 Talking

8*8 dot matrix: Does anyone have a finished 8*8 dot matrix package? Can you help me? Send it to my email: [email=yong27@163.com]yong27@163.com[/email] Thank you very much!!!...; yong27 PCB Design

My CPLD development board schematic.rar: My CPLD development board schematic diagram, study and learn...; 江汉大学南瓜 FPGA/CPLD

How to view the code size and RAM usage after MDK compilation?: How to check the code size and RAM usage after MDK compilation?As shown in the picture:How much RAM is there?What do RO, RW, and ZI mean? ?KEIL.JPG(23.63 KB)Downloads:0 2010-5-27 12:24...; Ericl stm32/stm8

I would like to ask about the problem of the flyback power supply making noise when the load is small: The flyback power supply has a sound problem when the load is small The main control is UC3842, the power supply can work normally, the output of pin 1 is normal when under load, there is a sound when...; 灞波儿奔 Power technology

2812 startup steps (refer to 28335): [size=4]Below is the flash boot process of 2812. You can refer to it to learn how to boot 28335. [/size] [size=4] [/size] [size=4]Detailed process description of 2812 booting from internal flash: [/si...; fish001 Microcontroller MCU

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components