W29N04GW/Z
W29N04GW/Z
4G-BIT 1.8V
NAND FLASH MEMORY
1
Release Date: May 21
th
, 2018
Revision A
W29N04GW/Z
Table of Contents
1.
2.
3.
GENERAL DESCRIPTION ............................................................................................................... 7
FEATURES ....................................................................................................................................... 7
PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 8
3.1
Pin Assignment 48 pin TSOP1 (x8) ...................................................................................... 8
3.2
Pin Assignment 63 ball VFBGA (x8) .................................................................................... 9
3.3
Pin Assignment 63 ball VFBGA (x16) ................................................................................ 10
3.4
Pin Descriptions .................................................................................................................. 11
PIN DESCRITPIONS ...................................................................................................................... 12
4.1
Chip Enable (#CE).............................................................................................................. 12
4.2
Write Enable (#WE) ............................................................................................................ 12
4.3
Read Enable (#RE) ............................................................................................................ 12
4.4
Address Latch Enable (ALE) .............................................................................................. 12
4.5
Command Latch Enable (CLE) .......................................................................................... 12
4.6
Write Protect (#WP)............................................................................................................ 12
4.7
Ready/Busy (RY/#BY) ........................................................................................................ 12
4.8
Input and Output (I/Ox) ....................................................................................................... 12
BLOCK DIAGRAM .......................................................................................................................... 13
MEMORY ARRAY ORGANIZATION .............................................................................................. 14
6.1
Array Organization (x8) ...................................................................................................... 14
6.2
Array Organization (x16) .................................................................................................... 15
MODE SELECTION TABLE ........................................................................................................... 16
COMMAND TABLE......................................................................................................................... 17
DEVICE OPERATIONS .................................................................................................................. 18
9.1
READ operation .................................................................................................................. 18
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.1.7
9.1.8
PAGE READ (00h-30h)......................................................................................................... 18
TWO PLANE READ (00h-00h-30h) ...................................................................................... 18
RANDOM DATA OUTPUT (05h-E0h) ................................................................................... 20
READ ID (90h) ...................................................................................................................... 21
READ PARAMETER PAGE (ECh) ....................................................................................... 22
READ STATUS (70h)............................................................................................................ 24
READ STATUS ENHANCED (78h) ...................................................................................... 25
READ UNIQUE ID (EDh) ...................................................................................................... 27
PAGE PROGRAM (80h-10h) ................................................................................................ 28
SERIAL DATA INPUT (80h).................................................................................................. 28
RANDOM DATA INPUT (85h) .............................................................................................. 29
TWO PLANE PAGE PROGRAM .......................................................................................... 29
READ for COPY BACK (00h-35h) ........................................................................................ 31
PROGRAM for COPY BACK (85h-10h) ................................................................................ 31
TWO PLANE READ for COPY BACK ................................................................................... 32
TWO PLANE PROGRAM for COPY BACK .......................................................................... 32
4.
5.
6.
7.
8.
9.
9.2
PROGRAM operation ......................................................................................................... 28
9.2.1
9.2.2
9.2.3
9.2.4
9.3
COPY BACK operation....................................................................................................... 31
9.3.1
9.3.2
9.3.3
9.3.4
9.4
BLOCK ERASE operation .................................................................................................. 36
Release Date: May 21
th
, 2018
2
Revision A
W29N04GW/Z
9.4.1
BLOCK ERASE (60h-D0h).................................................................................................... 36
9.4.2 TWO PLANE BLOCK ERASE .................................................................................................. 37
9.5
9.6
RESET operation................................................................................................................ 38
9.5.1
9.6.1
9.6.2
RESET (FFh) ........................................................................................................................ 38
GET FEATURES (EEh) ........................................................................................................ 42
SET FEATURES (EFh) ......................................................................................................... 43
FEATURE OPERATION..................................................................................................... 39
9.7
9.8
9.9
10.
ONE TIME PROGRAMMABLE (OTP) area ....................................................................... 44
WRITE PROTECT .............................................................................................................. 45
BLOCK LOCK ..................................................................................................................... 47
ELECTRICAL CHARACTERISTICS............................................................................................... 48
10.1 Absolute Maximum Ratings (1.8V) ..................................................................................... 48
10.2 Operating Ranges (1.8V) ................................................................................................... 48
10.3 Device Power-up Timing .................................................................................................... 49
10.4 DC Electrical Characteristics (1.8V) ................................................................................... 50
10.5 AC Measurement Conditions (1.8V) ................................................................................... 51
10.6 AC Timing Characteristics for Command, Address and Data Input (1.8V) ........................ 52
10.7 AC Timing Characteristics for Operation (1.8V) ................................................................. 53
10.8 Program and Erase Characteristics ................................................................................... 54
TIMING DIAGRAMS ....................................................................................................................... 55
INVALID BLOCK MANAGEMENT .................................................................................................. 63
12.1 Invalid Blocks...................................................................................................................... 63
12.2 Initial Invalid Blocks ............................................................................................................ 63
12.3 Error in Operation ............................................................................................................... 64
12.4 Addressing in Program Operation ...................................................................................... 65
PACKAGE DIMENSIONS ............................................................................................................... 66
13.1 TSOP 48-pin 12x20 ............................................................................................................ 66
13.2 Fine-Pitch Ball Grid Array 63-ball ....................................................................................... 67
ORDERING INFORMATION .......................................................................................................... 68
VALID PART NUMBERS ................................................................................................................ 69
REVISION HISTORY ...................................................................................................................... 70
11.
12.
13.
14.
15.
16.
3
Release Date: May 21
th
, 2018
Revision A
W29N04GW/Z
List of Tables
Table 3-1 Pin Descriptions .......................................................................................................................... 11
Table 6-1 Addressing .................................................................................................................................. 14
Table 6-2 Addressing .................................................................................................................................. 15
Table 7-1 Mode Selection ........................................................................................................................... 16
Table 8-1 Command Table ......................................................................................................................... 17
Table 9-1 Device ID and configuration codes for Address 00h .................................................................. 21
Table 9-2 ONFI Identifying Codes for Address 20h .................................................................................... 21
Table 9-3 Parameter Page Output Value .................................................................................................... 24
Table 9-4 Status Register Bit Definition ...................................................................................................... 25
Table 9-5 Features ...................................................................................................................................... 39
Table 9-6 Feature Address 80h .................................................................................................................. 40
Table 9-7 Feature Address 81h .................................................................................................................. 41
Table 10-1 Absolute Maximum Ratings ...................................................................................................... 48
Table 10-2 Operating Ranges ..................................................................................................................... 48
Table 10-3 DC Electrical Characteristics .................................................................................................... 50
Table 10-4 AC Measurement Conditions .................................................................................................... 51
Table 10-5 AC Timing Characteristics for Command, Address and Data Input ......................................... 52
Table 10-6 AC Timing Characteristics for Operation .................................................................................. 53
Table 10-7 Program and Erase Characteristics .......................................................................................... 54
Table 12-1 Valid Block Number .................................................................................................................. 63
Table 12-2 Block Failure ............................................................................................................................. 64
Table 15-1 Part Numbers for Industrial Temperature ................................................................................. 69
Table 16-1 History Table ............................................................................................................................. 70
4
Release Date: May 21
th
, 2018
Revision A
W29N04GW/Z
List of Figures
Figure 3-1 Pin Assignment 48-pin TSOP1 (Package code S) ...................................................................... 8
Figure 3-2 Pin Assignment 63-ball VFBGA (Package code B) ..................................................................... 9
Figure 3-3 Pin Assignment 63-ball VFBGA (Package code B) ................................................................... 10
Figure 5-1 NAND Flash Memory Block Diagram ........................................................................................ 13
Figure 6-1 Array Organization ..................................................................................................................... 14
Figure 6-2 Array Organization ..................................................................................................................... 15
Figure 9-1 Page Read Operations .............................................................................................................. 18
Figure 9-2 Two Plane Read Page (00h-00h-30h) Operation ...................................................................... 19
Figure 9-3 Random Data Output ................................................................................................................. 20
Figure 9-4 Two Plane Random Data Read (06h-E0h) Operation ............................................................... 20
Figure 9-5 Read ID ...................................................................................................................................... 21
Figure 9-6 Read Parameter Page ............................................................................................................... 22
Figure 9-7 Read Status Operation .............................................................................................................. 24
Figure 9-8 Read Status Enhanced (78h) Operation ................................................................................... 26
Figure 9-9 Read Unique ID ......................................................................................................................... 27
Figure 9-10 Page Program.......................................................................................................................... 28
Figure 9-11 Random Data Input ................................................................................................................. 29
Figure 9-12 Two Plane Page Program ....................................................................................................... 30
Figure 9-13 Program for Copy Back Operation .......................................................................................... 33
Figure 9-14 Copy Back Operation with Random Data Input ....................................................................... 33
Figure 9-15 Two Plane Copy Back ............................................................................................................. 34
Figure 9-16 Two Plane Copy Back with Random Data Input ..................................................................... 34
Figure 9-17 Two Plane Program for Copy Back ......................................................................................... 35
Figure 9-18 Block Erase Operation ............................................................................................................. 36
Figure 9-19 Two Plane Block Erase Operation........................................................................................... 37
Figure 9-20 Reset Operation....................................................................................................................... 38
Figure 9-21 Get Feature Operation ............................................................................................................. 42
Figure 9-22 Set Feature Operation ............................................................................................................. 43
Figure 9-23 Erase Enable ........................................................................................................................... 45
Figure 9-24 Erase Disable .......................................................................................................................... 45
Figure 9-25 Program Enable ....................................................................................................................... 46
Figure 9-26 Program Disable ...................................................................................................................... 46
Figure 9-27 Program for Copy Back Enable ............................................................................................... 46
Figure 9-28 Program for Copy Back Disable .............................................................................................. 47
Figure 10-1 Power ON/OFF Sequence ....................................................................................................... 49
Figure 11-1 Command Latch Cycle ............................................................................................................ 55
Figure 11-2 Address Latch Cycle ................................................................................................................ 55
Figure 11-3 Data Latch Cycle ..................................................................................................................... 56
Figure 11-4 Serial Access Cycle after Read ............................................................................................... 56
Figure 11-5 Serial Access Cycle after Read (EDO) .................................................................................... 57
Figure 11-6 Read Status Operation ............................................................................................................ 57
Figure 11-7 Page Read Operation .............................................................................................................. 58
Figure 11-8 #CE Don't Care Read Operation ............................................................................................. 58
Figure 11-9 Random Data Output Operation .............................................................................................. 59
Release Date: May 21
th
, 2018
Revision A
5
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