Integrated
Circuit
Systems, Inc.
ICS8304
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL F
ANOUT
B
UFFER
F
EATURES
•
4 LVCMOS / LVTTL outputs
•
LVCMOS / LVTTL clock input
•
Maximum output frequency: 200MHz
•
Output skew: 45ps (maximum at 3.3V supply)
•
Part-to-part skew: 500ps (maximum)
•
Small 8 lead SOIC package saves board space
•
3.3V input, outputs may be either 3.3V or 2.5V supply modes
•
Lead-Free package available
•
0°C to 70°C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS8304 is a low skew, 1-to-4 Fanout
Buffer and a member of the HiPerClockS
™
HiPerClockS™
family of High Performance Clock Solutions
from ICS. The ICS8304 is characterized at
full 3.3V for input V
DD
, and mixed 3.3V and 2.5V
for output operating supply modes (V
DDO
). Guaranteed out-
put and par t-to-par t skew character istics make the
ICS8304 ideal for those clock distribution applications
demanding well defined performance and repeatability.
ICS
B
LOCK
D
IAGRAM
Q0
P
IN
A
SSIGNMENT
V
DDO
V
DD
CLK
GND
1
2
3
4
8
7
6
5
Q3
Q2
Q1
Q0
Q1
CLK
Q2
ICS8304
8-Lead SOIC, 150mil
3.9mm x 4.9mm, x 1.63mm package body
M Package
Top View
Q3
8304AM
www.icst.com/products/hiperclocks.html
1
REV. F SEPTEMBER 13, 2004
Integrated
Circuit
Systems, Inc.
ICS8304
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL F
ANOUT
B
UFFER
Type
Power
Power
Input
Power
Output
Output
Output
Output
Pulldown
Description
Output supply pin.
Core supply pin.
LVCMOS / LVTTL clock input.
Power supply ground.
Single clock output. LVCMOS / LVTTL interface levels.
Single clock output. LVCMOS / LVTTL interface levels.
Single clock output. LVCMOS / LVTTL interface levels.
Single clock output. LVCMOS / LVTTL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7
8
Name
V
DDO
V
DD
CLK
GND
Q0
Q1
Q2
Q3
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pulldown Resistor
Output Impedance
Test Conditions
Minimum
Typical
4
V
DD
, V
DDO
= 3.465V
51
5
7
12
15
Maximum
Units
pF
pF
KΩ
Ω
8304AM
www.icst.com/products/hiperclocks.html
2
REV. F SEPTEMBER 13, 2004
Integrated
Circuit
Systems, Inc.
ICS8304
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL F
ANOUT
B
UFFER
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
112.7°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
15
8
Units
V
V
mA
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
Refer to NOTE 1
I
OH
= -16mA
I
OH
= -100uA
Refer to NOTE 1
V
OL
Output Low Voltage
I
OL
= 16mA
I
OL
= 100uA
-5
2.6
2.9
3
0.5
0.25
0.15
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
1.3
150
Units
V
V
µA
µA
V
V
V
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement Section, "3.3V Output Load Test Circuit".
T
ABLE
3C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
15
8
Units
V
V
mA
mA
8304AM
www.icst.com/products/hiperclocks.html
3
REV. F SEPTEMBER 13, 2004
Integrated
Circuit
Systems, Inc.
ICS8304
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL F
ANOUT
B
UFFER
Test Conditions
Minimum
2
-0.3
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-5
2.1
0.5
Typical
Maximum
V
DD
+ 0.3
1.3
150
Units
V
V
µA
µA
V
V
T
ABLE
3D. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
OL
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement Section,
"3.3V/2.5V Output Load Test Circuit".
T
ABLE
4A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
f
MAX
tp
LH
Maximum Output Frequency
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise Time
Output Fall Time
30% to 70%
30% to 70%
250
250
IJ 166MHz
166MHz < f
≤
189.5MHz
ƒ = 133MHz
2.0
2.0
Test Conditions
Minimum
Typical
Maximum
200
3.3
3.4
45
500
500
500
60
Units
MHz
ns
ns
ps
ps
ps
ps
%
t
sk(o)
t
sk(pp)
t
R
t
F
odc
Output Duty Cycle
f
≤
189.5MHz
40
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
4B. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
f
MAX
tp
LH
Maximum Output Frequency
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise Time
Output Fall Time
30% to 70%
30% to 70%
250
250
IJ 166MHz
166MHz < f
≤
189.5MHz
ƒ = 133MHz
2.3
2.15
Test Conditions
Minimum
Typical
Maximum
189.5
3.7
3.55
60
500
500
500
60
Units
MHz
ns
ns
ps
ps
ps
ps
%
t
sk(o)
t
sk(pp)
t
R
t
F
odc
Output Duty Cycle
f
≤
189.5MHz
40
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8304AM
www.icst.com/products/hiperclocks.html
4
REV. F SEPTEMBER 13, 2004
Integrated
Circuit
Systems, Inc.
ICS8304
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
1.65V±5%
2.05V±5%
1.25V±5%
V
DD
,
V
DDO
SCOPE
Qx
V
DD
V
DDO
Qx
SCOPE
LVCMOS
GND
LVCMOS
GND
-1.65V±5%
-1.25V±5%
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
V
DD
PART 1
Qx
V
DD
Qx
2
2
V
PART 2
Qy
DD
V
DD
Qy
2
t
sk(o)
2
t
sk(pp)
O
UTPUT
S
KEW
70%
30%
t
R
t
F
70%
P
ART
-
TO
-P
ART
S
KEW
V
Q0:Q3
DDO
2
Pulse Width
t
PERIOD
Clock
Outputs
30%
odc =
t
PW
t
PERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
CLK
V
DD
2
Q0:Q3
V
DDO
2
t
PD
P
ROPAGATION
D
ELAY
8304AM
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5
REV. F SEPTEMBER 13, 2004
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