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ICS8304AMLN

Description
LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
Categorysemiconductor    logic   
File Size145KB,9 Pages
ManufacturerISSI(Integrated Silicon Solution Inc.)
Websitehttp://www.issi.com/
Download Datasheet Parametric View All

ICS8304AMLN Overview

LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8

ICS8304AMLN Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals8
Maximum operating temperature70 Cel
Minimum operating temperature0.0 Cel
Maximum supply/operating voltage3.46 V
Minimum supply/operating voltage3.14 V
Rated supply voltage3.3 V
Processing package description3.90 × 4.90 MM, 1.63 MM HEIGHT, LEAD FREE, MS-012, SOIC-8
Lead-freeYes
EU RoHS regulationsYes
stateTRANSFERRED
packaging shapeRectangle
Package SizeSMALL OUTLINE
surface mountYes
Terminal formGULL WING
Terminal spacing1.27 mm
terminal coatingMATTE Tin
Terminal locationpair
Packaging MaterialsPlastic/Epoxy
Temperature levelCOMMERCIAL
Enter conditionsstandard
Logic IC typeLow Skew Clock Driver
Number of inverted outputs0.0
Real output number4
propagation delay TPD3.7 ns
Maximum same-side bending0.0600 ns
Integrated
Circuit
Systems, Inc.
ICS8304
L
OW
S
KEW
, 1-
TO
-4
LVCMOS / LVTTL F
ANOUT
B
UFFER
F
EATURES
4 LVCMOS / LVTTL outputs
LVCMOS / LVTTL clock input
Maximum output frequency: 200MHz
Output skew: 45ps (maximum at 3.3V supply)
Part-to-part skew: 500ps (maximum)
Small 8 lead SOIC package saves board space
3.3V input, outputs may be either 3.3V or 2.5V supply modes
Lead-Free package available
0°C to 70°C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS8304 is a low skew, 1-to-4 Fanout
Buffer and a member of the HiPerClockS
HiPerClockS™
family of High Performance Clock Solutions
from ICS. The ICS8304 is characterized at
full 3.3V for input V
DD
, and mixed 3.3V and 2.5V
for output operating supply modes (V
DDO
). Guaranteed out-
put and par t-to-par t skew character istics make the
ICS8304 ideal for those clock distribution applications
demanding well defined performance and repeatability.
ICS
B
LOCK
D
IAGRAM
Q0
P
IN
A
SSIGNMENT
V
DDO
V
DD
CLK
GND
1
2
3
4
8
7
6
5
Q3
Q2
Q1
Q0
Q1
CLK
Q2
ICS8304
8-Lead SOIC, 150mil
3.9mm x 4.9mm, x 1.63mm package body
M Package
Top View
Q3
8304AM
www.icst.com/products/hiperclocks.html
1
REV. F SEPTEMBER 13, 2004
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