Atmel ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
8-bit Atmel Microcontroller with 16/32/64KB In-System Programmable Flash
DATASHEET
Features
•
High performance, low power Atmel
®
AVR
®
8-Bit Microcontroller
•
Advanced RISC architecture
– 130 powerful instructions – most single clock cycle execution
– 32 × 8 general purpose working registers
– Fully static operation
– Up to 16MIPS throughput at 16MHz (Atmel ATmega165PA/645P)
– Up to 20MIPS throughput at 20MHz (Atmel
ATmega165A/325A/325PA/645A/3250A/3250PA/6450A/6450P)
– On-chip 2-cycle multiplier
•
High endurance non-volatile memory segments
– In-system self-programmable flash program memory
• 16KBytes (ATmega165A/ATmega165PA)
• 32KBytes (ATmega325A/ATmega325PA/ATmega3250A/ATmega3250PA)
• 64KBytes (ATmega645A/ATmega645P/ATmega6450A/ATmega6450P)
– EEPROM
• 512Bytes (ATmega165A/ATmega165PA)
• 1Kbytes (ATmega325A/ATmega325PA/ATmega3250A/ATmega3250PA)
• 2Kbytes (ATmega645A/ATmega645P/ATmega6450A/ATmega6450P)
– Internal SRAM
• 1KBytes (ATmega165A/ATmega165PA)
• 2KBytes (ATmega325A/ATmega325PA/ATmega3250A/ATmega3250PA)
• 4KBytes (ATmega645A/ATmega645P/ATmega6450A/ATmega6450P)
– Write/erase cycles: 10,000 flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
(1)
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True read-while-write operation
– Programming lock for software security
•
Atmel QTouch
®
library support
– Capacitive touch buttons, sliders and wheels
– Atmel QTouch and QMatrix acquisition
– Up to 64 sense channels
•
JTAG (IEEE std. 1149.1 compliant) interface
– Boundary-scan capabilities according to the JTAG standard
– Extensive on-chip debug support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
•
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real time counter with separate oscillator
– Four PWM channels
– 8-channel, 10-bit ADC
8285F–AVR–08/2014
– Programmable serial USART
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition detector
– Programmable Watchdog Timer with separate on-chip oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on pin change
•
Special microcontroller features
– Power-on reset and programmable Brown-out detection
– Internal calibrated oscillator
– External and internal interrupt sources
– Five sleep modes: Idle, ADC Noise Reduction, Power-save, Power-down and Standby
•
I/O and packages
– 54/69 programmable I/O lines
– 64/100-lead TQFP, 64-pad QFN/MLF and 64-pad DRQFN
•
Speed grade:
– ATmega 165A/165PA/645A/645P: 0 - 16MHz @ 1.8 - 5.5V
– ATmega325A/325PA/3250A/3250PA/6450A/6450P: 0 - 20MHz @ 1.8 - 5.5V
•
Temperature range:
– -40°C to 85°C industrial
•
Ultra-low power consumption (picoPower
®
devices)
– Active mode:
• 1MHz, 1.8V: 215µA
• 32kHz, 1.8V: 8µA (including oscillator)
– Power-down mode: 0.1µA at 1.8V
– Power-save mode: 0.6µA at 1.8V (Including 32kHz RTC)
Note:
1.
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
Atmel-8285F–AVR-ATmega–08/2014
2
1.
1.1
Pin configurations
Pinout - TQFP and QFN/MLF
64A (TQFP)and 64M1 (QFN/MLF) pinout Atmel
ATmega165A/ATmega165PA/ATmega325A/ATmega325PA/ATmega645A/ATmega645P.
56
PF5 (ADC5/TMS)
55
PF6 (ADC6/TDO)
57
PF4 (ADC4/TCK)
54
PF7 (ADC7/TDI)
Figure 1-1.
61
PF0 (ADC0)
60
PF1 (ADC1)
59
PF2 (ADC2)
58
PF3 (ADC3)
AVCC
AREF
53 GND
GND
52 VCC
51 PA0
50 PA1
64
63
62
49 PA2
48 PA3
47 PA4
46 PA5
45 PA6
44 PA7
43 PG2
42 PC7
41 PC6
40 PC5
39 PC4
38 PC3
37 PC2
36 PC1
35 PC0
34
33
PG1
PG0
DNC
(RXD/PCINT0) PE0
(TXD/PCINT1) PE1
(XCK/AIN0/PCINT2) PE2
(AIN1/PCINT3) PE3
(USCK/SCL/PCINT4) PE4
(DI/SDA/PCINT5) PE5
(DO/PCINT6) PE6
(CLKO/PCINT7) PE7
(SS/PCINT8) PB0
(SCK/PCINT9) PB1
(MOSI/PCINT10) PB2
(MISO/PCINT11) PB3
(OC0A/PCINT12) PB4
(OC1A/PCINT13) PB5
(OC1B/PCINT14) PB6
1
2
INDEX CORNER
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND 22
(TOSC2) XTAL2 23
(TOSC1) XTAL1 24
(ICP1) PD0 25
(INT0) PD1 26
PD2 27
PD3 28
(OC2A/PCINT15) PB7 17
(T1) PG3 18
(T0) PG4 19
RESET/PG5 20
VCC 21
PD4 29
PD5 30
PD6 31
Note: The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be soldered
or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the
board.
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
Atmel-8285F–AVR-ATmega–08/2014
PD7 32
3
1.2
Pinout - 100A (TQFP)
Pinout Atmel ATmega3250A/ATmega3250PA/ATmega6450A/ATmega6450P.
Figure 1-2.
TQFP
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF4 (ADC4/TCK)
PF7 (ADC7/TDI)
PH7 (PCINT23)
PH6 (PCINT22)
PH5 (PCINT21)
PH4 (PCINT20)
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
AGND
AVCC
AREF
GND
DNC
DNC
DNC
DNC
DNC
VCC
PA0
PA1
77
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
DNC
(RXD/PCINT0) PE0
(TXD/PCINT1) PE1
(XCK/AIN0/PCINT2) PE2
(AIN1/PCINT3) PE3
(USCK/SCL/PCINT4) PE4
(DI/SDA/PCINT5) PE5
(DO/PCINT6) PE6
(CLKO/PCINT7) PE7
VCC
GND
DNC
(PCINT24) PJ0
(PCINT25) PJ1
DNC
DNC
DNC
DNC
(SS/PCINT8) PB0
(SCK/PCINT9) PB1
(MOSI/PCINT10) PB2
(MISO/PCINT11) PB3
(OC0A/PCINT12) PB4
(OC1A/PCINT13) PB5
(OC1B/PCINT14) PB6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
INDEX CORNER
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PA2
PA3
PA4
PA5
PA6
PA7
PG2
PC7
PC6
DNC
PH3 (PCINT19)
PH2 (PCINT18)
PH1 (PCINT17)
PH0 (PCINT16)
DNC
DNC
DNC
DNC
PC5
PC4
PC3
PC2
PC1
PC0
PG1
PG0
RESET/PG5
(TOSC2) XTAL2
(TOSC1) XTAL1
(INT0) PD1
GND
(OC2A/PCINT15) PB7
(PCINT26) PJ2
(PCINT27) PJ3
(PCINT28) PJ4
(PCINT29) PJ5
(PCINT30) PJ6
(ICP1) PD0
VCC
DNC
DNC
(T1) PG3
(T0) PG4
DNC
PD2
PD3
PD4
PD5
PD6
DNC
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
Atmel-8285F–AVR-ATmega–08/2014
PD7
4
2.
Overview
The Atmel ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P is a low-power CMOS 8-bit
microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle,
this microcontroller achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power
consumption versus processing speed.
2.1
Block diagram
Block diagram.
Figure 2-1.
GND
VCC
PF0 - PF7
PA0 - PA7
PC0 - PC7
PORTF DRIVERS
PORTA DRIVERS
PORTC DRIVERS
DATA REGISTER
PORTF
DATA DIR.
REG. PORTF
DATA REGISTER
PORTA
DATA DIR.
REG. PORTA
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
8-BIT DATA BUS
AVCC
AGND
AREF
ADC
CALIB. OSC
INTERNAL
OSCILLATOR
OSCILLATOR
JTAG TAP
DATA DIR.
REG. PORTH
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
TIMING AND
CONTROL
PORTH DRIVERS
ON-CHIP DEBUG
PROGRAM
FLASH
SRAM
MCU CONTROL
REGISTER
PH0 - PH7
DATA REGISTER
PORTH
BOUNDARY-
SCAN
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
X
Y
Z
TIMER/
COUNTERS
PROGRAMMING
LOGIC
INSTRUCTION
DECODER
INTERRUPT
UNIT
RESET
DATA DIR.
REG. PORTD
DATA REG.
PORTG
DATA DIR.
REG. PORTG
PORTD DRIVERS
PORTG DRIVERS
PD0 - PD7
PG0 - PG4
DATA DIR.
REG. PORTJ
CONTROL
LINES
ALU
EEPROM
PORTJ DRIVERS
AVR CPU
STATUS
REGISTER
PJ0 - PJ6
DATA REGISTER
PORTJ
USART
UNIVERSAL
SERIAL INTERFACE
SPI
ANALOG
COMPARATOR
DATA REGISTER
PORTE
DATA DIR.
REG. PORTE
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTD
+
-
PORTE DRIVERS
PORTB DRIVERS
PE0 - PE7
PB0 - PB7
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one
single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
Atmel-8285F–AVR-ATmega–08/2014
XTAL1
XTAL2
5
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