Datasheet
R2A20169NP/SA/SP
8-bit 12ch D/A Converter with Buffer Amplifiers
R03DS0020EJ0300
Rev.3.00
Jul 25, 2013
Description
The R2A20169 is an integrated circuit semiconductor of CMOS structure with 12 channels of built in D/A
unnecessary and enabling configuration of a system with few component parts.
Serial data transfer type input can easily be used through a combination of three lines: DI, CLK, and LD.
Outputs incorporate buffer op-amps that have a drive capacity of 1 mA or above for both sink source, and
can operate over the entire voltage range from almost ground to Vcc ( 0 to 5V ), making peripheral elements
unnecessary and enabling configuration of a system with few component parts.
Very small QFN package is added to lineup. It is suitable for a small mounting and reduces the mounting area.
Features
·
Guarantee Nonlinearity error : +/-1.0LSB, Differential nonlinearity error : +/-0.7LSB
·
Data transfer format: 12-bit serial data input type by 3 wire ( DI, SCK, LD )
·
Output buffer op-amps: Operable over entire voltage range from almost ground to Vcc ( 0 to 5V )
·
High output current capacity: +/-1mA or Higher
·
Very small size package line-up: QFN-20 (pin pitch: 0.5mm), TSSOP-20 (pin pitch 0.65mm)
·
Conversion from digital data to analog control data for home-use and industrial equipment.
Application
Block Diagram
Number for TSSOP/SOP package
Number for QFN package
Ao12
Vcc
Ao11
GND
Ao2
Ao1
DI
CLK
LD
DO
20
18
19
17
18
16
17
15
16
14
15
13
14
12
13
11
12
10
11
9
12-bit shift register
D0 1 2 3 4 5 6 7
8-bit upper
segment R-2R
D/A converter
8-bit latch
D/A
8 9 10 11
D/A
D/A
Power on
reset
8
8-bit latch
Channel
decoder
8-bit latch
8-bit latch
12
8-bit latch
8-bit upper
segment R-2R
D/A converter
8-bit latch
8-bit latch
8-bit latch
8-bit latch
8-bit latch
8-bit latch
8-bit latch
D/A
D/A
D/A
D/A
D/A
D/A
D/A
19
20
1
2
3
4
5
6
7
8
1
V
refL
2
Ao3
3
Ao4
4
Ao5
5
Ao6
6
Ao7
7
Ao8
8
Ao9
9
Ao10
10
V
refU
Page 1 of 9
R03DS0020EJ0300 Rev.3.00
Jul 25, 2013
R2A20169NP/SA/SP
Datasheet
Pin Arrangement
R2A20169NP (Top view)
18
GND
19
V
refL
20
Ao3
17
Ao2
16
Ao1
R2A20169SP/SA (Top view)
V
refL
1
Ao3
2
15
DI
20
GND
19
Ao2
Ao4
1
R2A20169NP
Ao5
2
Ao6
3
Ao7
4
Ao8
5
Ao10
7
Ao11
10
Ao9
6
V
refU
8
Vcc
9
R2A20169SP/SA
Ao4
3
Ao5
4
Ao6
5
Ao7
6
Ao8
7
Ao9
8
Ao10
9
V
refU
10
18
Ao1
17
DI
16
CLK
15
LD
14
Do
13
Ao12
12
Ao11
11
Vcc
14
CLK
13
LD
12
Do
11
Ao12
Outline: PWQN0020KB-A [NP]
Outline: PRSP0020DD-B[SP]
PTSP0020JB-A [SA]
Pin Description
Pin No.
[QFN]
15
12
14
[TSSOP
/SOP]
17
14
16
Pin
Name
DI
Do
CLK
Function
Serial data input terminal.
(Input serial data with a 12-bit data length.)
Serial data output terminal
(Data is sequentially output from the MSB bit.)
Serial clock input terminal
(Input signal from DI terminal is input to 12-bit shift register at rise of serial clock.)
Load terminal
(When High level is input to LD terminal, value in 12-bit shift register is loaded
into decoder and 8-bit latch.)
13
16
17
20
1
2
3
4
5
6
7
10
11
9
18
8
19
15
18
19
2
3
4
5
6
7
8
9
12
13
11
20
10
1
LD
Ao1
Ao2
Ao3
Ao4
Ao5
Ao6
Ao7
Ao8
Ao9
Ao10
Ao11
Ao12
Vcc
GND
V
refU
V
refL
8-bit resolution D/A converter output terminals
(After power-on, all channels are reset and DAC data 00h is output.)
Power supply terminal
GND terminal
D/A converter upper reference voltage input terminal
D/A converter lower reference voltage input terminal
R03DS0020EJ0300 Rev.3.00
Jul 25, 2013
Page 2 of 9
R2A20169NP/SA/SP
Datasheet
(Ta= +25deg unless otherwise noted)
Absolute Maximum Ratings
Item
Supply voltage
D/A converter upper reference voltage
D/A converter lower reference voltage
Buffer amplifier output current
Input voltage
Output voltage
Power dissipation
Thermal derating factor
Operating temperature
Storage temperature
Symbol
Vcc
V
refU
V
refL
I
AO
Vin
Vo
Pd
K theta
Topr
Tstg
Conditions
Ratings
-0.3 to +6.5
-0.3 to +6.5
-0.3 to +6.5
Unit
V
V
V
mA
V
V
mW
mW/deg
deg
deg
Continuous
-2.0 to +2.0
-0.3 to Vcc+0.3 <+6.5
-0.3 to Vcc+0.3 <+6.5
Ta= +85deg
Ta> +25deg
290(NP) / 150(SA) / 300(SP)
7.25(NP) / 3.75(SA) / 7.5(SP)
-30 to +85
-40 to +125
Electrical Characteristics
« Digital Part »
Item
Supply voltage
Supply current
Input leak current
Input low voltage
Input high voltage
( Vcc, V
refU
= +5V +/-10%, Vcc>V
refU
, GND,V
refL
=0V, Ta= -30 to +85deg, Unless otherwise noted )
Limits
Symbol
Vcc
Icc
I
ILK
V
IL
4.0V < Vcc
V
IH
Vcc < 4.0V
4.0V < Vcc, I
OL
=2.0 mA
Output low voltage
Output high voltage
Supply voltage
rise time *1
Internal reset
operating voltage *1
Power supply restart
interval (Power supply
OFF
à
ON)
*1
V
OL
Vcc < 4.0V, I
OL
=1.5 mA
V
OH
I
OH
= -400 µA
Vcc = 0
®
2.7V
Vcc = 0
®
2.7V
-
Vcc – 0.4
100
-
-
-
-
1.5
0.4
-
-
1.9
V
V
µs
V
0.8Vcc
-
-
-
-
0.4
V
V
CLK = 1MHz, Vcc =5V, I
AO
=0µA
V
IN
= 0 to Vcc
Test conditions
Min
2.7
-
-10
-
0.5Vcc
Typ
5.0
0.6
-
-
-
Max
5.5
1.8
10
0.2Vcc
-
Unit
V
mA
µA
V
V
t
r
Vcc
Vcc
POR
t
POR
Vcc < 0.1V
1
-
-
ms
*1 : When power supply is turned on, internal circuit is initialized by power on reset circuit. But, if re-powered on quickly,
initialize is not operate. So, keep the time period of re-powered on (t
POR
).
tr
Vcc
t
POR
(equivalent to tr
Vcc
)
Vcc
Vcc
POR
GND
Internal
Reset signal
GND
< 0.1V
Resetting period
Resetting period
R03DS0020EJ0300 Rev.3.00
Jul 25, 2013
Page 3 of 9
R2A20169NP/SA/SP
Datasheet
« Analog Part »
Item
( Vcc,V
refU
= +5V +/-10%, Vcc>V
refU
, GND,V
refL
=0V, Ta= -30 to +85deg, unless otherwise noted )
Limits
Symbol
Test conditions
Min
Typ
1.5
-
-
-
-
-
-
-
-
-
-
-
-
5.0
Max
3.0
Vcc
V
Vcc < 4.5V
Vcc
³
4.5V
V
refL
Vcc < 4.5V
I
AO
= +/- 100 µA
V
AO
I
AO
= +/- 500 µA
I
AO
S
DL
S
L
S
ZERO
S
FULL
Co
Ro
Upper side saturation voltage = 0.3V,
Lower side saturation voltage = 0.2V
V
refU
=5V, V
refL
=0V, I
AO
=0µA,
Data condition: at maximum current
Unit
-
3.5
0.7Vcc
GND
GND
0.1
0.2
-1.0
-0.7
-1.0
-2.0
-2.0
-
-
mA
Current dissipation
D/A converter upper
reference voltage range *2
I
refU
Vcc
³
4.5V
V
refU
Vcc
Vcc-3.5
V
0.3Vcc
Vcc – 0.1
Vcc – 0.2
1.0
0.7
1.0
2.0
2.0
0.1
-
V
V
mA
LSB
LSB
LSB
LSB
µF
ohm
D/A converter lower
reference voltage range *2
Buffer amplifier output
voltage range
Buffer amplifier output
drive range
Differential nonlinearity
Nonlinearity
Zero code error
Full scale error
Output capacitive load
Buffer amplifier output
impedance
V
refU
= 4.79V,
V
refL
= 0.95V,
Vcc = 5.5V (15mV/LSB),
Without load (I
AO
=0µA)
*2 : The output does not necessary be the value with the reference voltage setting range.
The output value is determined by the buffer amplifier output voltage range (V
AO
).
R03DS0020EJ0300 Rev.3.00
Jul 25, 2013
Page 4 of 9
R2A20169NP/SA/SP
Datasheet
AC Characteristics
( Vcc, V
refU
= +5V +/-10%, Vcc >V
refU
, GND=V
refL
= 0V, Ta = -30 to +85deg, unless otherwise noted )
Item
Clock frequency
Clock low pulse width
Clock high pulse width
Clock rise time
Clock fall time
Data setup time
Data hold time
LD setup time
LD hold time
LD high pulse width
Data output delay time
D/A output settling time
Symbol
f
CLK
t
CKL
t
CKH
t
CR
t
CF
t
DCH
t
CHD
t
CHL
t
LDC
t
LDH
t
DO
t
LDD
C
L
< 100 pF
Ta=25deg, C
L
<100pF, V
AO
: 0.5¨4.5V,
The time until the output becomes the final
value of 1/2 LSB.
Test conditions
Limits
Min
-
40
40
-
-
4
30
40
40
40
-10
-
Typ
1.0
-
-
-
-
-
-
-
-
-
-
-
Max
10
-
-
200
200
-
-
-
-
-
50
150
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Timing Chart
t
CR
t
CKH
t
CF
CLK
t
CKL
DI
t
DCH
t
CHD
t
CHL
t
LDH
t
LDC
LD
t
LDD
D/A
output
t
Do
Do
output
(Note) Timing chart above is a schematic representation of the timing of each signal type.
CLK signal input is High or Low regardless, LD signal High input is enabled.
R03DS0020EJ0300 Rev.3.00
Jul 25, 2013
Page 5 of 9
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