Ultra-Low Capacitance TVS Diode Array
AOZ8000
General Description
The AOZ8000 is a transient voltage suppressor array
designed to protect high speed data lines from ESD and
lightning.
This device incorporates eight surge rated, low capaci-
tance steering diodes and a TVS in a single package.
During transient conditions, the steering diodes direct
the transient to either the positive side of the power
supply line or to ground. They may be used to meet the
ESD immunity requirements of IEC 61000-4-2, Level 4.
The TVS diodes provide effective suppression of ESD
voltages: ±15kV (air discharge) and ±8kV (contact
discharge).
The AOZ8000 comes in SOT-23, DFN-6, and SC-70
packages. They are compatible with both lead free and
SnPb assembly techniques. The small size, low capaci-
tance and high ESD protection makes it ideal for protect-
ing high speed video and data communication interfaces.
Features
●
ESD protection for high-speed data lines:
–
IEC 61000-4-2, level 4 (ESD) immunity test
–
±15kV (air discharge) and ±8kV (contact discharge)
–
IEC 61000-4-5 (Lightning) 5A (8/20µs)
–
Human Body Model (HBM) ±15kV
●
●
●
●
●
●
Small package saves board space
Low insertion loss
Protects four I/O lines
Low capacitance between I/O lines: 0.9pF
Low clamping voltage
Low operating voltage: 5.0V
Applications
●
●
●
●
●
●
USB 2.0 power and data line protection
Video graphics cards
Monitors and flat panel displays
Digital Video Interface (DVI)
10/100/1000 Ethernet
Notebook computers
Typical Application
USB Host
Controller
R
T
R
T
VBUS
+5V
Downstream
Ports
VBUS
D+
D-
AOZ8000
GND
+5V
VBUS
R
T
R
T
D+
D-
GND
Figure 1. 2 USB High Speed Ports
Rev. 2.4 July 2010
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Page 1 of 15
AOZ8000
Ordering Information
Part Number
AOZ8000HIL
AOZ8000DIL
AOZ8000CIL
Package
SC-70-6
DFN-6
SOT23-6
Environmental
RoHS Compliant
Green Prodcut
AOS Green Products (with “L” suffix) use reduced levels of Halogens, and are also RoHS compliant.
Please visit
www.aosmd.com/web/quality/rohs_compliant.jsp
for additional information.
Pin Configuration
CH1
1
6
CH4
CH1
1
6
CH4
VN
2
5
VP
VN
2
5
VP
CH2
3
4
CH3
CH2
3
4
CH3
SOT23-6/SC-70-6
(Top View)
DFN-6
(Top View)
Absolute Maximum Ratings
Exceeding the Absolute Maximum ratings may damage the device.
Parameter
VP – VN
Peak Pulse Current (I
PP
), t
P
= 8/20µs
Peak Power Dissipation (8 x 20µs@ 25°C)
SC-70
DFN
SOT-23
Storage Temperature (T
S
)
ESD Rating per IEC61000-4-2, Contact
(1)
ESD Rating per IEC61000-4-2, Air
(1)
ESD Rating per Human Body Model
(2)
Notes:
1. IEC 61000-4-2 discharge with C
Discharge
= 150pF, R
Discharge
= 330
Ω
.
2. Human Body Discharge per MIL-STD-883, Method 3015 C
Discharge
= 100pF, R
Discharge
= 1.5k
Ω
.
Rating
6V
5A
60W
70W
60W
-65°C to +150°C
±8kV
±15kV
±15kV
Maximum Operating Ratings
Parameter
Junction Temperature (T
J
)
Rating
-55°C to +125°C
Rev. 2.4 July 2010
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Page 2 of 15
AOZ8000
Electrical Characteristics
Symbol
V
RWM
V
BR
I
R
V
F
V
CL
Parameter
Reverse Working Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Diode Forward Voltage
Channel Clamp Voltage
Positive Transients
Negative Transient
Channel Clamp Voltage
Positive Transients
Negative Transient
Channel Clamp Voltage
Positive Transients
Negative Transient
Conditions
Between pin 5 and 2
(4)
I
T
= 1mA, between pins 5 and 2
(5)
V
RWM
= 5V, between pins 5 and 2
I
F
= 15mA
I
PP
= 1A, tp = 100ns, any I/O pin to
Ground
(3)(6)(8)
I
PP
= 5A, tp = 100ns, any I/O pin to
Ground
(3)(6)(8)
I
PP
= 12A, tp = 100ns, any I/O pin to
Ground
(3)(6)(8)
V
R
= 0V, f = 1MHz, any I/O pin to Ground
(3)(6)
V
R
= 0V, f = 1MHz, between I/O pins
(3)(6)
V
R
= 0V, f = 1MHz, any I/O pin to Ground
(3)(7)
Min.
6.6
Typ.
Max.
5.5
0.1
Units
V
V
µA
V
V
V
V
V
V
V
pF
pF
pF
pF
0.70
0.85
1
10.0
-3.0
11
-6.0
15.0
-10.0
C
j
Junction Capacitance
1.85
0.9
1.0
1.94
0.94
1.17
0.03
ΔC
j
Channel Input Capacitance
Matching
V
R
= 0V, f = 1MHz, between I/O pins
(3)(6)
Notes:
3. These specifications are guaranteed by design.
4. The working peak reverse voltage, V
RWM
, should be equal to or greater than the DC or continuous peak operating voltage level.
5. V
BR
is measured at the pulse test current I
T
.
6. Measurements performed with no external capacitor on V
P
(pin 5 floating).
7. Measurements performed with V
P
biased to 3.3 Volts (pin 5 @ 3.3V).
8. Measurements performed using a 100ns Transmission Line Pulse (TLP) system.
Rev. 2.4 July 2010
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Page 3 of 15
AOZ8000
Typical Performance Characteristics
Typical Variation of C
IN
vs V
R
(f = 1MHz, T = 25°C)
2.00
Input Capacitance (pF)
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
0.00
1.00
2.00
3.00
4.00
5.00
Vp (Pin 5) = 3.3V
Clamping Voltage vs. Peak Pulse Current
(tperiod = 100ns, tr = 1ns)
16
Clamping Voltage, V
CL
(V)
15
14
13
12
11
10
9
8
0
2
4
6
8
Peak Pulse Current, I
PP
(A)
10
12
Vp (Pin 5) = Float
Input Voltage (V)
Forward Voltage vs. Forward Current
(tperiod = 100ns, tr = 1ns)
12
10
8
6
4
2
0
2
4
6
8
10
12
1
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
I/O – Gnd Insertion Loss (S21) vs. Frequency
(Vp = 3.3V)
Forward Voltage (V)
Insertion Loss (dB)
10
100
Frequency (MHz)
1000
Forward Current (A)
I/O – I/O Insertion Loss (S21) vs. Frequency
(Vp = Float)
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
1
10
100
Frequency (MHz)
1000
20
0
-20
-40
-60
-80
10
Analog Crosstalk (I/O–I/O) vs. Frequency
Insertion Loss (dB)
Insertion Loss (dB)
100
Frequency (MHz)
1000
ESD Clamping
8kV Contact per IEC61000-4-2
Note: Data was taken with a 10X attenuator
Rev. 2.4 July 2010
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Page 4 of 15
AOZ8000
Application Information
The AOZ8000 TVS is design to protect four data lines
from fast damaging transient over-voltage by clamping it
to a reference. When the transient on a protected data
line exceed the reference voltage the steering diode is
forward bias thus, conducting the harmful ESD transient
away from the sensitive circuitry under protection.
PCB Layout Guidelines
Printed circuit board layout is the key to achieving the
highest level of surge immunity on power and data lines.
The location of the protection devices on the PCB is the
simplest and most important design rule to follow. The
AOZ8000 devices should be located as close as possible
to the noise source. The placement of the AOZ8000
devices should be used on all data and power lines that
enter or exit the PCB at the I/O connector. In most
systems, surge pulses occur on data and power lines
that enter the PCB through the I/O connector. Placing
the AOZ8000 devices as close as possible to the noise
source ensures that a surge voltage will be clamped
before the pulse can be coupled into adjacent PCB
traces. In addition, the PCB should use the shortest
possible traces. A short trace length equates to low
impedance, which ensures that the surge energy will be
dissipated by the AOZ8000 device. Long signal traces
will act as antennas to receive energy from fields that are
produced by the ESD pulse. By keeping line lengths as
short as possible, the efficiency of the line to act as an
antenna for ESD related fields is reduced. Minimize
interconnecting line lengths by placing devices with the
most interconnect as close together as possible. The
protection circuits should shunt the surge voltage to
either the reference or chassis ground. Shunting the
surge voltage directly to the IC’s signal ground can cause
ground bounce. The clamping performance of TVS
diodes on a single ground PCB can be improved by
minimizing the impedance with relatively short and wide
ground traces. The PCB layout and IC package parasitic
inductances can cause significant overshoot to the TVS’s
clamping voltage. The inductance of the PCB can be
reduced by using short trace lengths and multiple layers
with separate ground and power planes. One effective
method to minimize loop problems is to incorporate a
ground plane in the PCB design. The AOZ8000 ultra-low
capacitance TVS is designed to protect four high speed
data transmission lines from transient over-voltages by
clamping them to a fixed reference. The low inductance
and construction minimizes voltage overshoot during
high current surges. When the voltage on the protected
line exceeds the reference voltage the internal steering
diodes are forward biased, conducting the transient
current away from the sensitive circuitry.
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
1. Place the TVS near the IO terminals or connectors to
restrict transient coupling.
2. Fill unused portions of the PCB with ground plane.
3. Minimize the path length between the TVS and the
protected line.
4. Minimize all conductive loops including power and
ground loops.
5. The ESD transient return path to ground should be
kept as short as possible.
6. Never run critical signals near board edges.
7. Use ground planes whenever possible.
8. Avoid running critical signal traces (clocks, resets,
etc.) near PCB edges.
9. Separate chassis ground traces from components
and signal traces by at least 4mm.
10. Keep the chassis ground trace length-to-width ratio
<5:1 to minimize inductance.
11. Protect all external connections with TVS diodes.
Rev. 2.4 July 2010
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