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AD9530BCPZ

Description
IC CLOCK GEN 2.7GHZ
Categorysemiconductor    Analog mixed-signal IC   
File Size1017KB,41 Pages
ManufacturerADI
Websitehttps://www.analog.com
Environmental Compliance
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AD9530BCPZ Overview

IC CLOCK GEN 2.7GHZ

AD9530BCPZ Parametric

Parameter NameAttribute value
PLLyes
enterclock
outputCML
Number of circuits1
Ratio - Input:Output2:4
Differential - Input:OutputYes Yes
Frequency - maximum2.7GHz
Frequency divider/multiplieryes/no
Voltage - Power2.375 V ~ 2.625 V
Operating temperature-40°C ~ 85°C
Installation typesurface mount
Package/casing48-WFQFN Exposed Pad
Supplier device packaging48-LFCSP(7x7)
Data Sheet
FEATURES
4 CML Output, Low Jitter Clock Generator
with an Integrated 5.4 GHz VCO
AD9530
GENERAL DESCRIPTION
The
AD9530
is a fully integrated PLL and distribution supporting,
clock cleanup, and frequency translation device for 40 Gbps/
100 Gbps OTN applications. The internal PLL can lock to one
of two reference frequencies to generate four discrete output
frequencies up to 2.7 GHz.
The
AD9530
features an internal 5.11 GHz to 5.4 GHz, ultralow
noise voltage controlled oscillator (VCO). All four outputs are
individually divided down from the internal VCO using two high
speed VCO dividers (the Mx dividers) and four individual 8-bit
channel dividers (the Dx dividers). The high speed VCO dividers
offer fixed divisions of 2, 2.5, 3, and 3.5 for wide coverage of
possible output frequencies. The
AD9530
is configurable for
loop bandwidths <15 kHz to attenuate reference noise.
The
AD9530
is available in a 48-lead LFCSP and operates from a
single 2.5 V typical supply voltage.
The
AD9530
operates over the extended industrial temperature
range of −40°C to +85°C.
Fully integrated, ultralow noise phase-locked loop (PLL)
4 differential, 2.7 GHz common-mode logic (CML) outputs
2 differential reference inputs with programmable internal
termination options
<232 fs rms absolute jitter (12 kHz to 20 MHz) with a non-
ideal reference and 8 kHz loop bandwidth
<100 fs rms absolute jitter (12 kHz to 20 MHz) with an 80 kHz
loop bandwidth and low jitter input reference clock
Supports low loop bandwidths for jitter attenuation
Manual switchover
Single 2.5 V typical supply voltage
48-lead, 7 mm × 7 mm LFCSP
APPLICATIONS
40 Gbps/100 Gbps optical transport network (OTN) line side
clocking
Clocking of high speed analog-to-digital converters (ADCs)
and digital-to-analog converters (DACs)
Data communications
FUNCTIONAL BLOCK DIAGRAM
REF_SEL
AD9530
M1 DIVIDER
÷2, ÷2.5, ÷3, ÷3.5
PLL
M2 DIVIDER
÷2, ÷2.5, ÷3, ÷3.5
D1 DIVIDER
(1 TO 255)
D2 DIVIDER
(1 TO 255)
D3 DIVIDER
(1 TO 255)
D4 DIVIDER
(1 TO 255)
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
REFA
REFA
800MHz MAX
REFB
REFB
SERIAL PORT AND
CONTROL LOGIC
R DIVIDER
(1 TO 255)
SDIO SDO SCLK
CS
LD
CML 50Ω SOURCE TERMINATED
2.7GHz MAX
Figure 1.
Rev. 0
Document Feedback
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
14044-001

AD9530BCPZ Related Products

AD9530BCPZ AD9530BCPZ-REEL7
Description IC CLOCK GEN 2.7GHZ IC CLOCK GEN 2.7GHZ
PLL yes yes
enter clock clock
output CML CML
Number of circuits 1 1
Ratio - Input:Output 2:4 2:4
Differential - Input:Output Yes Yes Yes Yes
Frequency - maximum 2.7GHz 2.7GHz
Frequency divider/multiplier yes/no yes/no
Voltage - Power 2.375 V ~ 2.625 V 2.375 V ~ 2.625 V
Operating temperature -40°C ~ 85°C -40°C ~ 85°C
Installation type surface mount surface mount
Package/casing 48-WFQFN Exposed Pad 48-WFQFN Exposed Pad
Supplier device packaging 48-LFCSP(7x7) 48-LFCSP(7x7)

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