Enpirion
®
Power Datasheet
EN5322QI 2A PowerSoC
Synchronous Buck DC-DC Converter
with Integrated Inductor
General Description
The EN5322 is a high efficiency synchronous
buck converter with integrated inductor, PWM
controller, MOSFETS, and compensation
providing the smallest possible solution size.
The 4 MHz operation allows for the use of tiny
MLCC capacitors. It also enables a very wide
control loop bandwidth providing excellent
transient performance and reduced output
impedance. The internal compensation is
designed for unconditional stability across all
operating conditions.
Three VID output voltage select pins provide
seven pre-programmed output voltages along
with an option for external resistor divider.
Output voltage can be programmed on-the-fly to
provide fast, dynamic voltage scaling with
smooth transitions between VID programmed
output voltages.
Ordering Information
Part Number
Temp Rating (°C)
Package
EN5322QI
EVB-EN5322QI
-40 to +85
24-pin QFN T&R
QFN Evaluation Board
Features
•
Revolutionary Integrated Inductor
•
Total Solution Footprint as Small as 50 mm
2
•
4 mm x 6 mm x 1.1 mm QFN Package
•
4 MHz Fixed Switching Frequency
•
High Efficiency, up to 95 %
•
Low Ripple Voltage; 8 mV
P-P
Typical
•
2% Initial V
OUT
Accuracy with VID Codes
•
2% Initial 0.6 V Feedback Voltage Accuracy
•
2.4 V to 5.5 V Input Voltage Range
•
2 A Continuous Output Current Capability
•
Fast Transient Response
•
Low Dropout Operation: 100 % Duty Cycle
•
Power OK Signal with 5 mA Sink Capability
•
Dynamic Voltage Scaling with VID Codes
•
17
A
Typical Shutdown Current
•
Under Voltage Lockout, Over Current, Short
Circuit, and Thermal Protection
•
RoHS Compliant; MSL 3 260 °C Reflow
Applications
•
•
•
•
•
Point of Load Regulation for Low Power
Processors, Network Processors, DSPs’
FPGAs and ASICs
Replacement of LDOs
Noise Sensitive Applications such as A/V and
RF
Computing, Computer Peripherals, Storage,
Networking, and Instrumentation
DSL, STB, DVR, DTV, and iPC
Application Circuit
ON
V
IN
C
IN
10 uF
OFF
ENABLE
VSENSE
V
OUT
C
OUT
47 uF
PVIN
VS0
VS1
VOUT
EN5322
POK
PGND
AGND
VS2
PGND
AVIN
1 uF
Figure 1. Typical Application Circuit
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EN5322QI
Absolute Maximum Ratings
CAUTION:
Absolute maximum ratings are stress ratings only. Functional operation beyond recommended operating
conditions is not implied. Stress beyond absolute maximum ratings may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
Absolute Maximum Electrical Ratings
Voltages on: PVIN, AVIN, VOUT
Voltages on: VSENSE, VS0, VS1, VS2, ENABLE, POK
Voltage on: VFB
ESD Rating (Human Body Model)
ESD Rating (Charge Device Model)
-0.3 V
-0.3 V
-0.3 V
2 kV
500 V
-40 °C
-65 °C
MIN
6.5 V
V
IN
2.7 V
MAX
Absolute Maximum Thermal Ratings
Ambient Operating Range
Storage Temperature Range
Reflow Peak Body Temperature MSL3 (10 s)
+85 °C
+150 °C
+260 °C
Thermal Characteristics
TYP
MAX
Thermal Shutdown
T
SD
155
Thermal Shutdown Hysteresis
T
SDH
15
Thermal Resistance: Junction to Case (0 LFM)
6
JC
Thermal Resistance: Junction to Ambient (0 LFM)*
36
JA
* Based on a 2 oz. copper board and proper thermal design in line with JEDEC EIJ-JESD51 standards
PARAMETER
SYMBOL
MIN
UNITS
°C
°C
°C/W
°C/W
Recommended Operating Conditions
SYMBOL
MIN
Input Voltage Range
V
IN
2.4
Output Voltage Range
V
OUT
0.6
Output Current
I
LOAD
0
Operating Junction Temperature
T
J
-45
Note: V
DROPOUT
is defined as (I
LOAD
x Dropout Resistance) including temperature effect.
PARAMETER
V
IN
MAX
5.5
- V
DROPOUT
2
+125
UNITS
V
V
A
°C
Electrical Characteristics
V
IN
= 5 V and T
A
= 25 °C, unless otherwise noted.
PARAMETER
Operating Input Voltage
Under Voltage Lockout
UVLO Hysteresis
Output Voltage with VID
Codes (Note 1)
SYMBOL
TEST CONDITIONS
V
IN
going low to high
T
A
= 25 °C; V
IN
= 5V
I
LOAD
= 100 mA
VS2 VS1 VS0 VOUT (V)
0
0
0
3.3
0
0
1
2.5
0
1
0
1.8
0
1
1
1.5
1
0
0
1.25
1
0
1
1.2
1
1
0
0.8
V
IN
V
UVLO
MIN
2.4
TYP
2.2
0.15
MAX
5.5
UNITS
V
V
V
V
OUT
-2.0
-2.0
-2.0
-2.0
-2.0
-2.0
-2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
%
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EN5322QI
PARAMETER
VFB Voltage
Output Voltage with VID
Codes (Note 1)
SYMBOL
TEST CONDITIONS
T
A
= 25 °C; V
IN
= 5V
I
LOAD
= 100 mA, VS0 = VS1 = VS2 = 1
2.4 V
V
IN
5.5 V, I
LOAD
= 0 ~ 2 A,
-40°C
T
A
+85°C
VS2 VS1 VS0 VOUT (V)
0
0
0
3.3
0
0
1
2.5
0
1
0
1.8
0
1
1
1.5
1
0
0
1.25
1
0
1
1.2
1
1
0
0.8
2.4 V
V
IN
5.5 V, I
LOAD
= 0 ~ 2 A,
VS0 = VS1 = VS2 = 1,
-40°C
T
A
+85°C
Switching between VID settings
VID Mode VOUT Programming
VFB Mode VOUT Programming
-40°C
T
A
+85°C
Logic Low
Logic High
V
OUT
Rising
V
OUT
Falling
V
OUT
Rising
V
OUT
Falling
I
SINK
= 5 mA, -40°C
T
A
+85°C
POK High, -40°C
T
A
+85°C
ENABLE Low
No Switching
Switching, V
OUT
= 1.2 V
2.4 V
V
IN
5.5 V,
-40°C
T
A
+85°C
MIN
0.588
TYP
0.600
MAX
0.612
UNITS
V
V
FB
V
OUT
-3.0
-3.0
-3.0
-3.0
-3.0
-3.0
-3.5
+3.0
+3.0
+3.0
+3.0
+3.0
+3.0
+3.0
%
VFB Voltage
Dynamic Voltage Slew Rate
Soft Start Slew Rate
Soft Start Time
VFB, ENABLE, VS0-VS2
Pin Input Current (Note 2)
ENABLE, VS0-VS2 Voltage
Threshold
POK Upper Threshold
POK Upper Threshold
POK Lower Threshold
POK Lower Threshold
POK Low Voltage
POK Pin V
OH
Leakage
Current
Shutdown Current
Quiescent Current
Quiescent Current
Current Limit Threshold
PFET On Resistance
NFET On Resistance
Dropout Resistance
Operating Frequency
V
FB
0.582
0.975
0.975
0.78
0.600
1.5
1.5
1.2
0.618
2.025
2.025
1.62
+/-40
V
V/ms
V/ms
ms
nA
V
%
%
%
%
V
nA
A
A
mA
A
m
m
m
MHz
mV
P-P
mV
P-P
0.0
1.4
111
102
92
90
0.15
0.4
V
IN
0.4
500
17
800
15
2.1
3.0
160
60
200
4
14
8
300
F
OSC
C
OUT
= 1 x 47
F
1206 X5R MLCC,
V
OUT
= 1.2 V, I
LOAD
= 2 A
Output Ripple Voltage
V
RIPPLE
C
OUT
= 2 x 22
F
0805 X5R MLCC,
V
OUT
= 1.2 V, I
LOAD
= 2 A
Note 1: The tolerances hold true only if V
IN
is greater than (V
OUT
+ V
DROPOUT
).
Note 2: VFB, ENABLE, VS0-VS2 pin input current specification is guaranteed by design.
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Pin Configuration
Figure 2. Pin Diagram, Top View.
Pin Description
PIN
1, 21-24
NAME
NC(SW)
FUNCTION
No Connect. These pins are internally connected to the common drain output of the internal
MOSFETs. NC(SW) pins are not to be electrically connected to any external signal, ground, or
voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result
in part malfunction or damage.
Input/Output Power Ground. Connect these pins to the ground electrode of the input and
output filter capacitors. Refer to Layout Considerations section for details.
Voltage and Power Output. Connect these pins to output capacitor(s).
Output Voltage Select. These pins set one of seven preset output voltages and the external
divider option (refer to Electrical Characteristics table for more details), and can be directly
pulled up to V
IN
or pulled down to GND; these pins must not be left floating.
Sense Pin for Internally Programmed Output Voltages with VID Codes. For either VID code or
external resistor divider applications, connect this pin to the last local output filter capacitor for
internal compensation.
Feedback Pin for External Voltage Divider Network. Connect a resistor divider to this pin to set
the output voltage. Use 340 k, 1% or better for the upper resistor.
Analog Ground for the Controller Circuits
Analog Voltage Input for the Controller Circuits. Connect this pin to the input power supply.
Use a 1
F
bypass capacitor on this pin.
Power OK with an Open Drain Output. Refer to Power OK section.
Input Enable. A logic high signal on this pin enables the output and initiates a soft start. A
logic low signal disables the output and discharges the output to GND. The ENABLE pin
should not be left floating as it could be in an unknown and random state. It is recommended
to enable the device after both PVIN and AVIN is in regulation. See ENABLE operation for
details.
2-3, 8-9
4-7
10-12
PGND
VOUT
VS2-0
13
14
15
16
17
VSENSE
VFB
AGND
AVIN
POK
18
ENABLE
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EN5322QI
PIN
19-20
NAME
PVIN
FUNCTION
Input Power Supply. Connect to input supply. Decouple with input capacitor(s) to PGND.
Functional Block Diagram
POK
PVIN
UVLO
POK
Thermal Limit
Current Limit
ENABLE
Soft Start
P-Drive
(-)
PWM
Comp
(+)
NC (SW)
Logic
N-Drive
VOUT
PGND
VSENSE
Sawtooth
Generator
Compensation
Network
(-)
Error
Amp
(+)
Switch
VFB
DAC
VREF
Voltage
Select
Package Boundary
AVIN
AGND
VS0 VS1 VS2
BIAS
Figure 3. Functional Block Diagram.
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03454
March 15, 2018
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