DF2S5M4SL
ESD Protection Diodes
Silicon Epitaxial Planar
DF2S5M4SL
1. General
The DF2S5M4SL is a TVS diode (ESD protection diode) protects semiconductor devices used in mobile device
interfaces and other applications to protect against static electricity and noise.
Utilizing snapback characteristics, the DF2S5M4SL provides low dynamic resistance and superior protective
performance.
Furthermore, it is optimum the high speed signal application for the low capacitance performance. The
DF2S5M4SL is housed in an ultra-compact package (0.62 mm
×
0.32 mm) to meet applications that require a
small footprint.
2. Applications
Mobile Equipment
Smartphones
Tablets
Notebook PCs
Desktop PCs
Note:
This product is designed for protection against electrostatic discharge (ESD) and is not intended for any other
purpose, including, but not limited to, voltage regulation.
3. Features
(1)
(2)
(3)
(4)
(5)
Suitable for use with a 3.3 V signal line. (V
RWM
≤
3.6 V)
Protects devices with its high ESD performance.
(V
ESD
=
±20
kV (Contact / Air) @IEC61000-4-2)
Low dynamic resistance protects semiconductor devices from static electricity and noise.
(R
DYN
= 0.3
Ω
(typ.))
Snapback characteristics realizing low clamping voltage protects semiconductor devices.
(V
C
= 8 V@I
PP
= 2 A (typ.))
Compact package is suitable for use in high density board layouts such as in mobile devices.
(0.62 mm
×
0.32 mm size (Nickname: SL2))
4. Packaging
SL2
Start of commercial production
©2016-2018
Toshiba Electronic Devices & Storage Corporation
1
2016-03
2018-01-23
Rev.4.0
DF2S5M4SL
5. Example of Circuit Diagram
6. Quick Reference Data
Characteristics
Working peak reverse voltage
Total capacitance
Dynamic resistance
Electrostatic discharge voltage
(IEC61000-4-2) (Contact)
Symbol
V
RWM
C
t
R
DYN
V
ESD
(Note 2)
(Note 3)
Note
(Note 1)
Test Condition
V
R
= 0 V, f = 1 MHz
Min
Typ.
0.35
0.3
Max
3.6
0.5
20
Unit
V
pF
Ω
kV
Note 1: Recommended operating condition.
Note 2: TLP parameters: Z0 = 50
Ω,
tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of
dynamic resistance using least squares fit of TLP characteristics between I
PP1
= 8 A and I
PP2
= 16 A.
Note 3: Criterion: No damage to devices.
©2016-2018
Toshiba Electronic Devices & Storage Corporation
2
2018-01-23
Rev.4.0
DF2S5M4SL
6.1. ESD Clamp Waveform (Note)
Fig. 6.1.1 +8 kV
Fig. 6.1.2 -8 kV
Fig. 6.1.3 +15 kV
Fig. 6.1.4 -15 kV
Fig. 6.1.5 IEC61000-4-2 (Contact)
Note:
The above characteristics curves are presented for reference only and not guaranteed by production test,
unless otherwise noted.
©2016-2018
Toshiba Electronic Devices & Storage Corporation
3
2018-01-23
Rev.4.0
DF2S5M4SL
6.2. TLP Characteristics (Note)
Note:
The above characteristics curves are presented for reference only and not guaranteed by production test,
unless otherwise noted.
6.3. Clamp Voltage - Peak Pulse Current (V
C
- I
PP
) (Note)
Fig. 6.3.1 V
C
- I
PP
Note:
Fig. 6.3.2 Based on IEC61000-4-5 8/20
µ
s pulse.
The above characteristics curves are presented for reference only and not guaranteed by production test,
unless otherwise noted.
©2016-2018
Toshiba Electronic Devices & Storage Corporation
4
2018-01-23
Rev.4.0
DF2S5M4SL
7. Absolute Maximum Ratings (Note) (Unless otherwise specified, T
a
= 25
)
Characteristics
Electrostatic discharge voltage (IEC61000-4-2) (Contact)
Electrostatic discharge voltage (IEC61000-4-2) (Air)
Peak pulse power (tp = 8/20
µs)
Peak pulse current (tp = 8/20
µs)
Junction temperature
Storage temperature
P
PK
I
PP
T
j
T
stg
(Note 2)
Symbol
V
ESD
Note
(Note 1)
Rating
±20
±20
30
2
150
-55 to 150
W
A
Unit
kV
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 1: According to IEC61000-4-2.
Note 2: According to IEC61000-4-5.
Note:
8. Electrical Characteristics (Unless otherwise specified, T
a
= 25
)
V
RWM
: Working peak reverse voltage
V
BR
: Reverse breakdown voltage
I
BR
: Reverse breakdown current
I
R
: Reverse current
V
C
: Clamp voltage
I
PP
: Peak pulse current
R
DYN
: Dynamic resistance
V
F
: Forward voltage
Fig. 8.1 Definitions of Electrical Characteristics
Characteristics
Working peak reverse voltage
Total capacitance
Dynamic resistance
Reverse breakdown voltage
Reverse current
Clamp voltage
Symbol
V
RWM
C
t
R
DYN
V
BR
I
R
V
C
Note
(Note 1)
(Note 2)
Test Condition
V
R
= 0 V, f = 1 MHz
I
BR
= 1 mA
V
RWM
= 3.6 V
Min
3.7
Typ.
0.35
0.3
4.3
6
8
14
18
Max
3.6
0.5
5.5
0.1
15
Unit
V
pF
Ω
V
µA
V
V
(Note 3)
(Note 2)
I
PP
= 1 A
I
PP
= 2 A
I
TLP
= 16 V
I
TLP
= 30 V
Note 1: Recommended operating condition.
Note 2: TLP parameters: Z0 = 50
Ω,
tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of
dynamic resistance using least squares fit of TLP characteristics between I
PP1
= 8 A and I
PP2
= 16 A.
Note 3: Based on IEC61000-4-5 8/20
µs
pulse.
©2016-2018
Toshiba Electronic Devices & Storage Corporation
5
2018-01-23
Rev.4.0
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