PI7C9X112SL
PCI Express-to-PCI Bridge
Datasheet
January 2017
Revision 1.4
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17-0016
PI7C9X112SL
PR
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Copyright © 2016, Diodes Incorporated
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January 2017
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PI7C9X112SL
PR
REVISION HISTORY
DATE
09/27/2008
04/28/2009
09/10/2009
11/10/2009
02/09/2010
04/21/2016
01/25/2017
REVISION #
0.2
0.3
1.0
1.1
1.2
1.3
1.4
DESCRIPTION
Preliminary release of PI7C9X112SL datasheet
Revised General Features and Part Ordering Info
Production release of PI7C9X112SL datasheet
Updated Section 2.2 PCI Express Signal Section
Removed reverse mode related description
Updated Section 2.5 JTAG Boundary Scan Signals
Updated Logo
Added Table 14-4 PCI Express Interface - Differential Transmitter (TX) Output
Characteristics
Added Table 14-5 PCI Express Interface - Differential Receiver (RX) Input
Characteristics
Added Section 14.4 Operating Ambient Temperature
Updated Section 2.8 Pin Assignments
Updated Section 14.1 Absolute Maximum Ratings
Updated Section 14.2 DC Specifications
PREFACE
The datasheet of PI7C9X112SL will be enhanced periodically when updated information is available. The
technical information in this datasheet is subject to change without notice. This document describes the
functionalities of PI7C9X112SL (PCI Express Bridge) and provides technical information for designers to design
their hardware using PI7C9X112SL.
Page 3 of 75
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Rev 1.4
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January 2017
© Diodes Incorporated
PI7C9X112SL
PR
TABLE OF CONTENTS
1
INTRODUCTION ........................................................................................................................ 10
1.1
1.2
1.3
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
3
3.1
3.2
4
4.1
4.2
5
5.1
5.2
5.3
PCI EXPRESS FEATURES ................................................................................................... 10
PCI FEATURES ..................................................................................................................... 11
GENERAL FEATURES ......................................................................................................... 11
SIGNAL TYPES ..................................................................................................................... 12
PCI EXPRESS SIGNALS ...................................................................................................... 12
PCI SIGNALS ........................................................................................................................ 12
MODE SELECT AND STRAPPING SIGNALS ................................................................... 14
JTAG BOUNDARY SCAN SIGNALS .................................................................................. 14
MISCELLANEOUS SIGNALS ............................................................................................. 14
POWER AND GROUND PINS ............................................................................................. 14
PIN ASSIGNMENTS ............................................................................................................. 15
FUNCTIONAL MODE SELECTION .................................................................................... 16
PIN STRAPPING ................................................................................................................... 16
TLP STRUCTURE ................................................................................................................. 17
VIRTUAL ISOCHRONOUS OPERATION .......................................................................... 18
CONFIGURATION REGISTER MAP .................................................................................. 19
PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP ............................................ 21
PCI CONFIGURATION REGISTERS .................................................................................. 23
VENDOR ID – OFFSET 00h ................................................................................................................ 23
DEVICE ID – OFFSET 00h .................................................................................................................. 23
COMMAND REGISTER – OFFSET 04h .............................................................................................. 23
PRIMARY STATUS REGISTER – OFFSET 04h ................................................................................... 24
REVISION ID REGISTER – OFFSET 08h ........................................................................................... 24
CLASS CODE REGISTER – OFFSET 08h ........................................................................................... 25
CACHE LINE SIZE REGISTER – OFFSET 0Ch .................................................................................. 25
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch .................................................................. 25
PRIMARY HEADER TYPE REGISTER – OFFSET 0Ch ...................................................................... 25
RESERVED REGISTERS – OFFSET 10h TO 17h ................................................................................ 25
PRIMARY BUS NUMBER REGISTER – OFFSET 18h ........................................................................ 26
SECONDARY BUS NUMBER REGISTER – OFFSET 18h .................................................................. 26
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h .............................................................. 26
SECONDARY LATENCY TIME REGISTER – OFFSET 18h................................................................ 26
I/O BASE REGISTER – OFFSET 1Ch .................................................................................................. 26
I/O LIMIT REGISTER – OFFSET 1Ch ................................................................................................. 26
SECONDARY STATUS REGISTER – OFFSET 1Ch ............................................................................ 26
MEMORY BASE REGISTER – OFFSET 20h ....................................................................................... 27
MEMORY LIMIT REGISTER – OFFSET 20h ...................................................................................... 27
PIN DEFINITIONS ...................................................................................................................... 12
MODE SELECTION AND PIN STRAPPING.......................................................................... 16
FORWARD (PCIE TO PCI) BRIDGING ................................................................................. 17
CONFIGURATION REGISTER ACCESS ............................................................................... 19
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
5.3.10
5.3.11
5.3.12
5.3.13
5.3.14
5.3.15
5.3.16
5.3.17
5.3.18
5.3.19
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© Diodes Incorporated
PI7C9X112SL
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5.3.20
5.3.21
5.3.22
5.3.23
5.3.24
5.3.25
5.3.26
5.3.27
5.3.28
5.3.29
5.3.30
5.3.31
5.3.32
5.3.33
5.3.34
5.3.35
5.3.36
5.3.37
5.3.38
5.3.39
5.3.40
5.3.41
5.3.42
5.3.43
5.3.44
5.3.45
5.3.46
5.3.47
5.3.48
5.3.49
5.3.50
5.3.51
5.3.52
5.3.53
5.3.54
5.3.55
5.3.56
5.3.57
5.3.58
5.3.59
5.3.60
5.3.61
5.3.62
5.3.63
5.3.64
5.3.65
5.3.66
5.3.67
5.3.68
5.3.69
5.3.70
5.3.71
5.3.72
5.3.73
PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h ......................................................... 27
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h ........................................................ 28
PREFETCHABLE BASE UPPER 32-BIT REGISTER – OFFSET 28h................................................. 28
PREFETCHABLE LIMIT UPPER 32-BIT REGISTER – OFFSET 2Ch ............................................... 28
I/O BASE UPPER 16-BIT REGISTER – OFFSET 30h ......................................................................... 28
I/O LIMIT UPPER 16-BIT REGISTER – OFFSET 30h........................................................................ 28
CAPABILITY POINTER – OFFSET 34h .............................................................................................. 28
EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h ....................................................... 28
INTERRUPT LINE REGISTER – OFFSET 3Ch ................................................................................... 29
INTERRUPT PIN REGISTER – OFFSET 3Ch ..................................................................................... 29
BRIDGE CONTROL REGISTER – OFFSET 3Ch ................................................................................ 29
PCI DATA BUFFERING CONTROL REGISTER – OFFSET 40h ....................................................... 30
CHIP CONTROL 0 REGISTER – OFFSET 40h ................................................................................... 31
RESERVED REGISTER – OFFSET 44h............................................................................................... 32
ARBITER ENABLE REGISTER – OFFSET 48h ................................................................................... 33
ARBITER MODE REGISTER – OFFSET 48h ...................................................................................... 33
ARBITER PRIORITY REGISTER – OFFSET 48h ................................................................................ 34
RESERVED REGISTERS – OFFSET 4Ch ............................................................................................ 34
MEMORY READSMART BASE LOWER 32-Bit REGISTER 1 – OFFSET 50h.................................... 35
MEMORY READSMART BASE UPPER 32-Bit REGISTER 1 – OFFSET 54h .................................... 35
MEMORY READSMART RANGE CONTROL REGISTER 1 – OFFSET 58h ...................................... 35
MEMORY READSMART BASE LOWER 32-Bit REGISTER 2 – OFFSET 5Ch ................................... 35
MEMORY READSMART BASE UPPER 32-Bit REGISTER 2 – OFFSET 60h .................................... 35
MEMORY READSMART RANGE SIZE REGISTER 2 – OFFSET 64h ................................................ 35
EXPRESS TRANSMITTER/RECEIVER REGISTER – OFFSET 68h .................................................... 36
UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER – OFFSET 68h ....................... 37
RESERVED REGISTER – OFFSET 6Ch .............................................................................................. 37
EEPROM AUTOLOAD CONTROL/STATUS REGISTER – OFFSET 70h ........................................... 37
RESERVED REGISTER – OFFSET 74h............................................................................................... 37
GPIO DATA AND CONTROL REGISTER – OFFSET 78h .................................................................. 38
RESERVED REGISTER – OFFSET 7Ch .............................................................................................. 38
PCI-X CAPABILITY ID REGISTER – OFFSET 80h ............................................................................ 38
NEXT CAPABILITY POINTER REGISTER – OFFSET 80h ................................................................ 38
PCI-X SECONDARY STATUS REGISTER – OFFSET 80h .................................................................. 38
PCI-X BRIDGE STATUS REGISTER – OFFSET 84h .......................................................................... 39
UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h ........................................................ 39
DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch ................................................. 40
POWER MANAGEMENT ID REGISTER – OFFSET 90h .................................................................... 40
NEXT CAPABILITY POINTER REGISTER – OFFSET 90h ................................................................ 40
POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 90h .................................................. 40
POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h .............................. 41
PCI-TO-PCI SUPPORT EXTENSION REGISTER – OFFSET 94h ..................................................... 41
RESERVED REGISTERS – OFFSET 98h – 9Ch .................................................................................. 42
CAPABILITY ID REGISTER – OFFSET A0h ....................................................................................... 42
NEXT POINTER REGISTER – OFFSET A0h....................................................................................... 42
SLOT NUMBER REGISTER – OFFSET A0h ....................................................................................... 42
CHASSIS NUMBER REGISTER – OFFSET A0h ................................................................................. 42
SECONDARY CLOCK AND CLKRUN CONTROL REGISTER – OFFSET A4h ................................. 42
CAPABILITY ID REGISTER – OFFSET A8h ....................................................................................... 43
NEXT POINTER REGISTER – OFFSET A8h....................................................................................... 43
RESERVED REGISTER – OFFSET A8h .............................................................................................. 43
SUBSYSTEM VENDOR ID REGISTER – OFFSET ACh ...................................................................... 44
SUBSYSTEM ID REGISTER – OFFSET ACh ...................................................................................... 44
PCI EXPRESS CAPABILITY ID REGISTER – OFFSET B0h .............................................................. 44
Page 5 of 75
PI7C9X112SL
Rev 1.4
17-0016
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January 2017
© Diodes Incorporated
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