74LVC1G80GV,125 datasheet, PDF

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74LVC1G80GV,125: DescriptionIC FF D-TYPE SNGL 1BIT 5TSOP; Categorylogic logic; File Size823KB，21 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com; Environmental Compliance

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74LVC1G80GV,125 Overview

IC FF D-TYPE SNGL 1BIT 5TSOP

74LVC1G80GV,125 Parametric

Parameter Name	Attribute value
Brand Name	Nexperia
Is it Rohs certified?	conform to
Maker	Nexperia
Parts packaging code	TSOP
package instruction	TSSOP,
Contacts	5
Manufacturer packaging code	SOT753
Reach Compliance Code	compliant
Factory Lead Time	8 weeks
Samacsys Description	74LVC1G80 - Single D-type flip-flop; positive-edge trigger@en-us
series	LVC/LCX/Z
JESD-30 code	R-PDSO-G5
JESD-609 code	e3
length	2.9 mm
Logic integrated circuit type	D FLIP-FLOP
Humidity sensitivity level	1
Number of digits	1
Number of functions	1
Number of terminals	5
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output polarity	INVERTED
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	13 ns
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	1.65 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.95 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Trigger type	POSITIVE EDGE
width	1.5 mm
minfmax	200 MHz

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74LVC1G80

Single D-type flip-flop; positive-edge trigger

Rev. 13 — 5 December 2016

Product data sheet

1. General description

The 74LVC1G80 provides a single positive-edge triggered D-type flip-flop.

Information on the data input is transferred to the Q output on the LOW-to-HIGH transition

of the clock pulse. The input pin D must be stable one set-up time prior to the

LOW-to-HIGH clock transition for predictable operation.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this

device in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using I

OFF

. The I

OFF

circuitry disables the output, preventing the damaging backflow current through the device

when it is powered down.

2. Features and benefits



Wide supply voltage range from 1.65 V to 5.5 V



High noise immunity



Complies with JEDEC standard:



JESD8-7 (1.65 V to 1.95 V)



JESD8-5 (2.3 V to 2.7 V)



JESD8B/JESD36 (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V



24

mA output drive (V

= 3.0 V)



CMOS low power consumption



Latch-up performance exceeds 250 mA



Direct interface with TTL levels



Inputs accept voltages up to 5 V



Multiple package options



Specified from

40 C

to +85

C

and

40 C

to +125

C.

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