*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted, V
F
= 1.0 V Max. @ I
F
= 10 mA for all types)
V
RWM
(V)
Device*
ESD9L3.3ST5G
ESD9L5.0ST5G
Device
Marking
6**
D
Max
3.3
5.0
I
R
(mA)
@ V
RWM
Max
1.0
1.0
V
BR
(V) @ I
T
(Note 2)
Min
4.8
5.4
I
T
mA
1.0
1.0
C (pF)
Typ
0.5
0.5
Max
0.9
0.9
V
C
(V)
@ I
PP
= 1 A
Max
9.0
9.8
V
C
Per IEC61000−4−2
(Note 4)
Figures 1 and 2
See Below
Figures 1 and 2
See Below
* Include S-prefix devices where applicable.
**Rotated 180°.
2. V
BR
is measured with a pulse test current I
T
at an ambient temperature of 25°C.
3. Surge current waveform per Figure 5.
4. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC61000−4−2
http://onsemi.com
2
ESD9L, SESD9L Series
IEC 61000−4−2 Spec.
Test
Voltage
(kV)
2
4
6
8
First Peak
Current
(A)
7.5
15
22.5
30
Current at
30 ns (A)
4
8
12
16
Current at
60 ns (A)
2
4
6
8
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
I @ 30 ns
IEC61000−4−2 Waveform
I
peak
100%
90%
Level
1
2
3
4
Figure 3. IEC61000−4−2 Spec
ESD Gun
TVS
Oscilloscope
50
W
Cable
50
W
Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D
−
Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
100
% OF PEAK PULSE CURRENT
90
80
70
60
50
40
30
20
10
0
0
20
t
P
t
r
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
PEAK VALUE I
RSM
@ 8
ms
PULSE WIDTH (t
P
) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8
ms
HALF VALUE I
RSM
/2 @ 20
ms
40
t, TIME (ms)
60
80
Figure 5. 8 X 20
ms
Pulse Waveform
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3
ESD9L, SESD9L Series
PACKAGE DIMENSIONS
SOD−923
CASE 514AB
ISSUE B
D
−X−
−Y−
E
1
2
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
DIM
A
b
c
D
E
H
E
L
MILLIMETERS
MIN
NOM MAX
0.34
0.37
0.40
0.15
0.20
0.25
0.07
0.12
0.17
0.75
0.80
0.85
0.55
0.60
0.65
0.95
1.00
1.05
0.05
0.10
0.15
MIN
0.013
0.006
0.003
0.030
0.022
0.037
0.002
INCHES
NOM
0.015
0.008
0.005
0.031
0.024
0.039
0.004
MAX
0.016
0.010
0.007
0.033
0.026
0.041
0.006
b
2X
0.08 (0.0032) X Y
A
c
L
H
E
SOLDERING FOOTPRINT*
0.90
0.40
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor
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