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74HC08D

Description
AND Gate 4-Element 2-IN CMOS 14-Pin SOIC T/R
Categorylogic    logic   
File Size180KB,8 Pages
ManufacturerToshiba Semiconductor
Websitehttp://toshiba-semicon-storage.com/
Environmental Compliance
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74HC08D Overview

AND Gate 4-Element 2-IN CMOS 14-Pin SOIC T/R

74HC08D Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerToshiba Semiconductor
package instructionSOP,
Reach Compliance Codeunknown
Factory Lead Time12 weeks
seriesHC/UH
JESD-30 codeR-PDSO-G14
length8.65 mm
Logic integrated circuit typeAND GATE
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
propagation delay (tpd)135 ns
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)4.5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.9 mm
Base Number Matches1
74HC08D
CMOS Digital Integrated Circuits Silicon Monolithic
74HC08D
1. Functional Description
Quad 2-Input AND Gate
2. General
The 74HC08D is a high speed CMOS 2-INPUT AND GATE fabricated with silicon gate C
2
MOS technology.
It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power
dissipation.
The internal circuit is composed of 2-stages including buffer output, which provide high noise immunity and
stable output.
All inputs are equipped with protection circuits against static discharge or transient excess voltage.
3. Features
(1)
(2)
(3)
(4)
High speed: t
pd
= 6 ns (typ.) at V
CC
= 5 V
Low power dissipation: I
CC
= 1.0
µA
(max) at T
a
= 25
Balanced propagation delays: t
PLH
t
PHL
Wide operating voltage range: V
CC(opr)
= 2.0 to 6.0 V
4. Packaging
SOIC14
Start of commercial production
©2016 Toshiba Corporation
1
2016-05
2016-08-04
Rev.4.0

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Description AND Gate 4-Element 2-IN CMOS 14-Pin SOIC T/R AND Gate 4-Element 2-IN CMOS 14-Pin SOIC T/R
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