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SI1013-C-GM2

Description
IC RF TXRX+MCU ISM<1GHZ 42-VFLGA
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size4MB,384 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance
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SI1013-C-GM2 Overview

IC RF TXRX+MCU ISM<1GHZ 42-VFLGA

SI1013-C-GM2 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Reach Compliance Codecompliant
Is SamacsysN
Has ADCYES
Address bus width
bit size8
maximum clock frequency25 MHz
DMA channelNO
External data bus width
length7 mm
Number of I/O lines15
Number of terminals42
PWM channelYES
encapsulated codeHLGA
Package shapeRECTANGULAR
Package formGRID ARRAY, HEAT SINK/SLUG
rom(word)8192
speed25 MHz
Maximum supply voltage3.6 V
Minimum supply voltage1.8 V
Nominal supply voltage1.9 V
surface mountYES
technologyCMOS
Terminal formBUTT
Terminal pitch0.5 mm
Terminal locationBOTTOM
width5 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER
Base Number Matches1
Si1010/1/2/3/4/5
Ultra Low Power, 64/32 kB, 10-Bit ADC
MCU with Integrated 240–960 MHz EZRadioPRO
®
Transceiver
Ultra Low Power: 0.9 to 3.6 V Operation
-
Typical sleep mode current < 0.1 µA; retains state and
-
-
-
-
EZRadioPRO
®
Transceiver
-
-
-
-
-
Frequency range = 240–960 MHz
Sensitivity = –121 dBm
FSK, GFSK, and OOK modulation
Max output power = +20 dBm (Si1010/1), +13 dBm
(Si1012/3/4/5)
RF power consumption
-
18.5 mA receive
-
18 mA @ +1 dBm transmit
-
30 mA @ +13 dBm transmit
-
85 mA @ +20 dBm transmit (Si1010/1)
Data rate = 0.123 to 256 kbps
Auto-frequency calibration (AFC)
Antenna diversity and transmit/receive switch control
Programmable packet handler
TX and RX 64 byte FIFOs
Frequency hopping capability
On-chip crystal tuning
RAM contents over full supply range; fast wakeup of < 2 µs
Less than 600 nA with RTC running
Less than 1 µA with RTC running and radio state retained
On-chip dc-dc converter allows operation down to 0.9 V.
Two built-in brown-out detectors cover sleep and active
modes
10-Bit or 12-Bit Analog to Digital Converter
-
Up to 300 ksps
-
Up to 18 external inputs
-
External pin or internal VREF (no external capacitor
-
-
-
required)
Built-in temperature sensor
External conversion start input option
Autonomous burst mode with 16-bit automatic averaging
accumulator
Dual Comparators
-
Programmable hysteresis and response time
-
Configurable as interrupt or reset source
-
Low current (< 0.5 µA)
On-Chip Debug
-
On-chip debug circuitry facilitates full-speed, non-intrusive
-
-
-
High-Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of instruc-
-
-
Memory
-
768 bytes RAM 16 kB (Si1010/2/4) or 8 kB (Si1011/3/5)
Flash; In-system programmable
tions in 1 or 2 system clocks
Up to
25 MIPS
throughput with 25 MHz clock
Expanded interrupt handler
in-system debug (No emulator required)
Provides breakpoints, single stepping
Inspect/modify memory and registers
Complete development kit
-
-
-
-
-
-
-
Digital Peripherals
-
12 port I/O plus 3 GPIO pins; Hardware enhanced UART,
-
-
SPI, and I
2
C serial ports available concurrently
Low power 32-bit SmaRTClock
Four general purpose 16-bit counter/timers; six channel
programmable counter array (PCA)
Clock Sources
-
Precision internal oscillators: 24.5 MHz with ±2% accuracy
-
-
-
supports UART operation; spread-spectrum mode for
reduced EMI; Low power 20 MHz internal oscillator
External oscillator: Crystal, RC, C, CMOS clock
SmaRTClock oscillator: 32.768 kHz crystal or self-oscillate
Can switch between clock sources on-the-fly; useful in
power saving modes and in implementing various power
saving modes
Package
-
42-pin LGA (5 x 7 mm)
Temperature Range: –40 to +85 °C
ANALOG
PERIPHERALS
A
M
U
X
DIGITAL I/O
UART
SMBus
SPI
PCA
Timer 0
Timer 1
Timer 2
Timer 3
CRC
Port 0
CROSSBAR
EZRadio
PRO
Serial
Interface
Port 1
Port 2
EZRadioPRO
(240–960 MHz)
LNA
12/10-bit
75/300 ksps
ADC
+
IREF
+
PA
TEMP
SENSOR
VREF
VREG
VOLTAGE
COMPARATORS
Mixer
PGA
ADC
24.5 MHz PRECISION
INTERNAL OSCILLATOR
External Oscillator
20 MHz LOW POWER
INTERNAL OSCILLATOR
HARDWARE smaRTClock
Digital
Modem
Delta
Sigma
Modulator
Digital
Logic
HIGH-SPEED CONTROLLER CORE
16/8 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
768 B SRAM
POR
WDT
PLL
OSC
Rev. 1.2 2/13
Copyright © 2013 by Silicon Laboratories
Si1010/1/2/3/4/5

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