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DS1100U-40+

Description
IC DELAY LINE 5TAP 40NS 8UMAX
Categorylogic    logic   
File Size119KB,7 Pages
ManufacturerMaxim
Websitehttps://www.maximintegrated.com/en.html
Environmental Compliance
Download Datasheet Parametric View All

DS1100U-40+ Overview

IC DELAY LINE 5TAP 40NS 8UMAX

DS1100U-40+ Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerMaxim
Parts packaging codeSOIC
package instructionTSSOP, TSSOP8,.19
Contacts8
Reach Compliance Codecompliant
ECCN codeEAR99
Factory Lead Time6 weeks
series1100
JESD-30 codeS-PDSO-G8
JESD-609 codee3
length3 mm
Logic integrated circuit typeSILICON DELAY LINE
Humidity sensitivity level1
Number of functions1
Number of taps/steps5
Number of terminals8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output impedance nominal value (Z0)50 Ω
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP8,.19
Package shapeSQUARE
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply5 V
Maximum supply current (ICC)50 mA
programmable delay lineNO
Prop。Delay @ Nom-Sup40 ns
Certification statusNot Qualified
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
Total delay nominal (td)40 ns
width3 mm
Base Number Matches1
19-5735; Rev 3/11
DS1100
5-Tap Economy Timing Element (Delay Line)
GENERAL DESCRIPTION
The DS1100 series delay lines have five equally
spaced taps providing delays from 4ns to 500ns.
These devices are offered in surface-mount
packages to save PCB area. Low cost and
superior reliability over hybrid technology is
achieved by the combination of a 100% silicon
delay line and industry-standard
µMAX
and SO
packaging. The DS1100 5-tap silicon delay line
reproduces the input-logic state at the output after
a fixed delay as specified by the extension of the
part number after the dash. The DS1100 is
designed to reproduce both leading and trailing
edges with equal precision. Each tap can drive up
to 10 74LS loads.
Maxim can customize standard products to meet
special needs.
FEATURES
All-Silicon Timing Circuit
Five Taps Equally Spaced
5V Operation
Delays are Stable and Precise
Both Leading- and Trailing-Edge Accuracy
Improved Replacement for DS1000
Low-Power CMOS
TTL/CMOS-Compatible
Vapor-Phase, IR, and Wave Solderable
Custom Delays Available
Fast-Turn Prototypes
Delays Specified Over Both Commercial and
Industrial Temperature Ranges
PIN ASSIGNMENT
IN
TAP 2
TAP 4
GND
1
2
3
4
8
7
6
5
V
CC
TAP 1
TAP 3
TAP 5
DS1100Z SO (150 mils)
DS1100U
µMAX®
PIN DESCRIPTION
TAP 1 to TAP 5
V
CC
GND
IN
- TAP Output Number
- +5V
- Ground
- Input
µ
MAX is a registered trademark of Maxim Integrated Products, Inc.
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