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ATAVRXPLAIN: DescriptionKIT EVAL FOR ATXMEGA128A1; CategoryDevelopment board/suite/development tools; File Size211KB，13 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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KIT EVAL FOR ATXMEGA128A1

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Board type	Evaluation platform
type	MCU 16-bit
core processor	AVR
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platform	XMEGA-A1 Xplained
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Installation type	fixed
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AVR1010: Minimizing the power consumption of

Atmel AVR XMEGA devices

Features

•

Sleep modes

Clock prescaling and source switching

Power Reduction Registers

RTC clock source

State of digital I/O

Watchdog

Brown Out Detector

JTAG interface

8-bit

Microcontrollers

Application Note

Preliminary

1 Introduction

The Atmel

AVR

XMEGA

devices are capable of achieving extremely low power

consumption, which is required by both portable electronics and other battery-

powered applications.

To reach the lowest possible power figures there are a few points to pay attention

to – it is not only the sleep mode that defines the power consumption, but also the

state of the I/O pins, the number of enabled peripheral modules and so on.

This application note describes what must be done to achieve the lowest possible

power consumption for XMEGA devices. Example code is also supplied, which

compiles with both GCC and IAR Embedded Workbench

Figure 1-1.

The XMEGA devices can achieve powers that are barely measurable.

Rev. 8267B-AVR-12/10

2 Reducing the power consumption to a minimum

Though many factors affect the power consumption, some will naturally affect more

than others. Listed below are the most important factors, with recommendations and

considerations.

2.1 Operating voltage

The power consumption is proportional to the square of the device’s supply voltage,

which should therefore be kept as low as possible.

A reduction in supply voltage can lower the limit for the maximum system clock

frequency, thus increasing the time required in ACTIVE mode to execute a given

amount of code.

Minimize power consumption by using as low supply voltage as possible.

2.2 Active mode operation

In ACTIVE mode, i.e. when sleep modes are not used, the power consumption is

proportional to the system clock frequency. This means that if sleep modes are not

used, the device should be run at the lowest possible system clock frequency to

minimize the power consumption.

Minimize power consumption by keeping the clock frequency as low as possible if

sleep modes are not used.

2.3 Sleep modes

In most applications it is desirable to minimize the power consumption, but not to

reduce the system clock frequency – mainly to ensure fast processing and quick

response of the system/product. In such applications one can use the “sleep modes”

of the Atmel

AVR

XMEGA

to put the device in a low power state when there is

nothing to process. The main principle is then to run as fast as possible, and sleep as

much as possible. Running as fast as possible reduces the effect of static power

consumption (i.e. independent of clock frequency), e.g. due to non-volatile memory

being enabled in ACTIVE mode.

The power consumption and operation of peripherals in sleep depends on which

sleep mode is used. Table 2-1 shows the characteristics of the different sleep modes

available for XMEGA devices. An application may switch between sleep modes

during operation, depending on which mode is the most suitable at the time.

AVR1010

8267B-AVR-12/10

Minimize power consumption by using the deepest allowable sleep modes at any

time, and running as fast as possible to minimize time spent in ACTIVE mode.

2.4 Clock Prescaling

Although it is recommended to run the CPU as fast as possible to minimize the time

spent in ACTIVE mode, there are situations where it is better to reduce the clock rate.

These situations commonly involve waiting in ACTIVE or IDLE mode for something

that takes a fixed amount of time, e.g. serial communication. In these cases, one

should avoid generating higher CPU and peripheral clock frequencies than are

needed for the active peripherals. This may be achieved by using clock prescaling,

which can be changed without causing glitches in the clock signal.

If prescaling is done internally in several peripherals, power can be conserved by

prescaling with the largest common factor as early as possible in the clock distribution

chain. This principle is illustrated in Figure 2-1.

Figure 2-1:

Peripherals without and with common prescaling by largest factor.

Peripheral w/

prescaling by

Peripheral w/

no prescaling

System

clock

prescaling

Peripheral

clock

Peripheral w/

prescaling by

System

clock

Prescaling by

Peripheral

clock

Peripheral w/

prescaling by

Peripheral w/

prescaling by

256

Peripheral w/

prescaling by

Note that since the prescaling also affects the CPU clock, it might not always be

desirable to perform this common prescaling in ACTIVE mode because computations

will take longer.

Minimize power consumption by actively using prescaling, especially when waiting in

ACTIVE or IDLE mode.

2.5 Clock Source Switching

One should avoid generating higher system clock rates than are actually needed. In

the ideal case, prescaling is unnecessary. This can be achieved by switching

between clock sources.

As an example, it is preferable to generate a 16MHz system clock by use of the PLL

with the 2MHz RC oscillator as reference, rather than the 32MHz RC oscillator with

prescaling to 16MHz. External clock sources may also be a good choice, especially if

they are already available in the system and therefore come with no extra “cost”.

The wake-up delay for the device depends on which clock source is used for the

system clock. One way to reduce this delay is to switch between clock sources so

that the device goes to sleep and wakes up with a fast-responding clock source.

AVR1010

8267B-AVR-12/10

AVR1010

Minimize power consumption by switching clock sources rather than relying on

prescaling alone for reducing clock rates.

2.6 Wake-Up Delays

When the device wakes up from sleep modes deeper than IDLE (with the exception

of the two STANDBY-modes), the system clock source must stabilize before the CPU

starts to operate. This introduces a short delay which depends on the selected clock

source. If an internal RC oscillator or external clock is used, the start-up delay is 6

cycles. This is in addition to the RC oscillator start-up time. If the XTAL oscillator is

used, the start-up delay is configurable. If frequency stability is wanted, it is

recommended with start-up delays of 1,000 cycles for ceramic resonators and

16,000cycles for quartz crystals respectively. This is in addition to the oscillator start-

up time, which will depend on the resonator and load capacitances.

In addition, there is a 13 cycle minimum delay before an Interrupt Service Routine

(ISR) starts executing after wake-up. This is due to, e.g. the program counter being

pushed on stack and the jump to the ISR.

During the start-up delay the power consumption is close to the power consumption in

IDLE, and thus represents “inefficient” power. If possible, it is therefore recommended

to wake up as seldom as possible and rather “do more” every time the device wakes

up.

To minimize the wake-up delay and conserve power, use an RC oscillator or external

clock source, and wake up as seldom as possible.

2.7 Power Reduction Registers

Most peripherals and internal modules can be individually stopped to avoid that these

draw power in ACTIVE mode and in IDLE sleep. This is done by setting their

respective bits in the Power Reduction Registers (PRR), which causes them to be

disconnected from the peripheral clock domain. It is required to disable modules and

peripherals via their respective control registers before setting their PRR bit, for the

Power Reduction to be effective. Some modules must be reinitialized after clearing

their PRR bit. Please refer to the sections about the individual PRR-bits in the

datasheet manual for more information.

In POWER-SAVE and POWER-DOWN the modules are stopped regardless of the

PRRs, since the peripheral clock domain is disabled.

To minimize power consumption, use the PRRs to disable peripherals and modules

that are not used.

2.8 RTC Clock Source

One of the reasons for using IDLE, POWER-SAVE and EXTENDED STANDBY is

that the RTC and its clock are active in these sleep modes. The RTC is commonly

used to wake the device up at timed intervals.

For most Atmel

AVR

XMEGA-families, three different oscillators can be used to

clock the RTC: An external 32kHz crystal, the internal 32kHz RC oscillator and the

internal 32kHz Ultra Low Power (ULP) oscillator. In all cases, a prescaled 1kHz clock

signal is available and should be used for reduced power consumption. For the

external 32kHz crystal oscillator, a special low power mode is also available

(X32KLPM).

8267B-AVR-12/10

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