HFBR-1312T Transmitter Output Optical Power and Dynamic Characteristics
Condition
Parameter
Peak Power
62.5/125
m
NA = 0.275
Symbol
P
T62
Min.
-16.0
-17.5
-15.5
-17.0
Typ.
[1]
-14.0
-13.5
-17.0
-16.5
5
1.8
2.2
Max.
-12.5
-11.5
-12.0
-11.0
-14.5
-13.5
-14.0
-13.0
10
4.0
4.0
Unit
dBm
T
A
25° C
0-70° C
25° C
0-70° C
I
F, peak
75 mA
75 mA
100 mA
100 mA
75 mA
75 mA
100 mA
100 mA
75 mA
75 mA
75 mA
Ref.
Notes 3, 4, 5
Fig. 4
Peak Power
50/125
m
NA = 0.20
P
T50
-19.5
-21.0
-19.0
-20.5
dBm
25° C
0-70° C
25° C
0-70° C
Notes 3, 4, 5
Fig. 4
Optical Overshoot
Rise Time
Fall Time
OS
t
r
t
f
%
ns
ns
0-70° C
0-70° C
0-70° C
Note 6
Fig. 5
Note 7
Fig. 5
Note 7
Fig. 5
Notes:
1. Typical data are at T
A
= 25° C.
2. Thermal resistance is measured with the transmitter coupled to a connector assembly and mounted on a printed circuit board;
JC
<
JA
.
3. Optical power is measured with a large area detector at the end of 1 meter of mode stripped cable, with an ST* precision ceramic ferrule
(MILSTD-83522/13), which approximates a standard test connector. Average power measurements are made at 12.5 MHz with a 50% duty cycle
drive current of 0 to I
F,peak
; I
F,average
= I
F,peak
/2. Peak optical power is 3 dB higher than average optical power.
4. When changing from
W
to dBm, the optical power is referenced to 1 mW (1000
W).
Optical power P(dBm) = 10*log[P(W)/1000W].
5. Fiber NA is measured at the end of 2 meters of mode stripped fiber using the far-field pattern. NA is defined as the sine of the half angle, determined
at 5% of the peak intensity point. When using other manufacturer’s fiber cable, results will vary due to differing NA values and test methods.
6. Overshoot is measured as a percentage of the peak amplitude of the optical waveform to the 100% amplitude level. The 100% amplitude level is
determined at the end of a 40 ns pulse, 50% duty cycle. This will ensure that ringing and other noise sources have been eliminated.
7. Optical rise and fall times are measured from 10% to 90% with 62.5/125
m
fiber. LED response time with recommended test circuit (Figure 3) at
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