BUJD103AD
11 October 2016
NPN power transistor with integrated diode
Product data sheet
1. General description
High voltage, high speed, planar passivated NPN power switching transistor with integrated anti-
parallel E-C diode in a SOT428 (DPAK) surface mountable plastic package.
2. Features and benefits
•
•
•
•
•
Fast switching
High voltage capability
Integrated anti-parallel E-C diode
Surface mountable package
Very low switching and conduction losses
3. Applications
•
•
•
•
DC-to-DC converters
Electronic lighting ballasts
Inverters
Motor control systems
4. Pinning information
Table 1. Pinning information
Pin
1
2
3
mb
Symbol Description
B
C
E
C
base
collector[1]
emitter
mounting base; connected to
collector
1
2
3
Simplified outline
mb
Graphic symbol
C
B
E
sym131
DPAK (SOT428)
[1]
it is not possible to make a connection to pin 2 of the SOT428 (DPAK) package
WeEn Semiconductors
BUJD103AD
NPN power transistor with integrated diode
5. Ordering information
Table 2. Ordering information
Type number
BUJD103AD
Package
Name
DPAK
Description
plastic single-ended surface-mounted package (DPAK); 3 leads
(one lead cropped)
Version
SOT428
BUJD103AD
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©
WeEn Semiconductors Co., Ltd. 2016. All rights reserved
Product data sheet
11 October 2016
2 / 12
WeEn Semiconductors
BUJD103AD
NPN power transistor with integrated diode
6. Limiting values
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CESM
V
CBO
V
CEO
I
C
I
CM
I
B
I
BM
P
tot
T
stg
T
j
10
I
C
(A)
8
I
Bon
V
BB
L
B
DUT
001aab999
Parameter
collector-emitter peak
voltage
collector-base voltage
collector-emitter voltage
collector current
peak collector current
base current
peak base current
total power dissipation
storage temperature
junction temperature
Conditions
V
BE
= 0 V
I
E
= 0 A
I
B
= 0 A
DC;
Fig. 1; Fig. 2; Fig. 3
Fig. 1; Fig. 2; Fig. 3
DC
T
mb
≤ 25 °C;
Fig. 4
Min
-
-
-
-
-
-
-
-
-65
-
Max
700
700
400
4
8
2
4
80
150
150
Unit
V
V
V
A
A
A
A
W
°C
°C
001aac000
V
CC
L
C
V
CL(CE)
probe point
6
4
2
Fig. 2. Test circuit for reverse bias safe operating area
0
0
200
400
600
800
1000
V
CEclamp
(V)
Fig. 1. Reverse bias safe operating area
BUJD103AD
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©
WeEn Semiconductors Co., Ltd. 2016. All rights reserved
Product data sheet
11 October 2016
3 / 12
WeEn Semiconductors
BUJD103AD
NPN power transistor with integrated diode
10
2
I
C
(A)
10
I
CM(max)
I
C(max)
1
(1)
001aac001
duty cycle = 0.01
II
(3)
t
p
= 20 µs
50 µs
100 µs
200 µs
500 µs
DC
(2)
10
- 1
I
(3)
10
- 2
III
(3)
10
- 3
1
10
10
2
10
3
V
CEclamp
(V)
1)Ptot maximum and Ptot peak maximum lines
2)Second breakdown limits
3) I = Region of permissable DC operation
II = Extension for repetitive pulse operation
III = Extension during turn-on in single transistor converters
provided that RBE ≤ 100 Ω and tp ≤ 0.6 μs
Fig. 3. Forward bias safe operating area for Tmb ≤ 25 °C
120
P
der
(%)
80
001aab993
40
0
0
40
80
120
T
mb
(°C)
160
Fig. 4. Normalized total power dissipation as a function of mounting base temperature
BUJD103AD
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©
WeEn Semiconductors Co., Ltd. 2016. All rights reserved
Product data sheet
11 October 2016
4 / 12
WeEn Semiconductors
BUJD103AD
NPN power transistor with integrated diode
7. Thermal characteristics
Table 4. Thermal characteristics
Symbol
R
th(j-mb)
Parameter
thermal resistance
from junction to
mounting base
thermal resistance
from junction to
ambient free air
10
Z
th(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
10
- 1
0.05
0.02
0.01
t
p
10
- 2
10
- 5
t
T
10
P
tot
δ=
t
p
T
Conditions
Fig. 5
Min
-
Typ
-
Max
1.56
Unit
K/W
R
th(j-a)
printed circuit board (FR4) mounted;
minimum footprint;
Fig. 6
-
75
-
K/W
001aab998
10
- 4
10
- 3
10
- 2
10
- 1
1
t
p
(s)
Fig. 5. Transient thermal impedance from junction to mounting base as a function of pulse width
7.0
7.0
2.15
2.5
1.5
4.57
001aab021
Fig. 6. Minimum footprint SOT428
BUJD103AD
All information provided in this document is subject to legal disclaimers.
©
WeEn Semiconductors Co., Ltd. 2016. All rights reserved
Product data sheet
11 October 2016
5 / 12
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