Fully Accurate 16-Bit V
OUT
nanoDAC
™
SPI Interface 2.7 V to 5.5 V, in an SOT-23
AD5062
FEATURES
Single 16-bit DAC, 1 LSB INL
Power-on reset to midscale or zero-scale
Guaranteed monotonic by design
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
Tiny 8-lead SOT-23 package, low power
Fast settling time of 4 μs typically
2.7 V to 5.5 V power supply
Low glitch on power-up
Unbuffered voltage capable of driving 60 kΩ load
SYNC interrupt facility
FUNCTIONAL BLOCK DIAGRAM
V
REF
V
DD
POWER-ON
RESET
BUF
AD5062
DAC
REGISTER
REF(+)
DAC
V
OUT
AGND
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
04766-001
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
SYNC
SCLK
DIN
DACGND
Figure 1.
Table 1. Related Devices
Part No.
AD5061
AD5063
AD5040/AD5060
Description
2.7 V to 5.5 V, 16-bit
nanoDAC
D/A,
4 LSBs INL, SOT-23.
2.7 V to 5.5 V, 16-bit
nanoDAC
D/A,
1 LSB INL, MSOP.
2.7 V to 5.5 V, 14-/16-bit
nanoDAC
D/A,
1 LSB INL, SOT-23.
GENERAL DESCRIPTION
The AD5062, a member of ADI’s
nanoDAC
family, is a low
power, single 16-bit unbuffered voltage-out DAC that operates
from a single 2.7 V to 5.5 V supply. The part offers a relative
accuracy specification of ±1 LSB, and operation is guaranteed
monotonic with a ±1 LSB DNL specification. The part uses a
versatile 3-wire serial interface that operates at clock rates up
to 30 MHz, and is compatible with standard SPI®, QSPI™,
MICROWIRE™, and DSP interface standards. The reference for
the AD5062 is supplied from an external V
REF
pin. A reference
buffer is also provided on-chip. The part incorporates a power-
on reset circuit that ensures the DAC output powers up to zero
scale or mid-scale and remains there until a valid write takes
place to the device. The part contains a power-down feature
that reduces the current consumption of the device to typically
300 nA at 5 V and provides software-selectable output loads
while in power-down mode. The part is put into power-down
mode over the serial interface. Total unadjusted error for the
part is <0.8 mV.
This part exhibits very low glitch on power-up.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
Available in a tiny 8-lead SOT-23 package.
16-bit accurate, 1 LSB INL.
Low glitch on power-up.
High speed serial interface with clock speeds up to 30 MHz.
Three power-down modes available to the user.
Reset to known output voltage (zero-scale or mid-scale).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2009 Analog Devices, Inc. All rights reserved.
AD5062
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics..................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 13
Theory of Operation ...................................................................... 14
DAC Architecture ....................................................................... 14
Reference Buffer ......................................................................... 14
Serial Interface ............................................................................ 14
Input Shift Register .................................................................... 14
SYNC Interrupt .......................................................................... 14
Power-On to Midscale or Zero Scale ....................................... 15
Software Reset ............................................................................. 15
Power-Down Modes .................................................................. 15
Microprocessor Interfacing ....................................................... 15
Applications..................................................................................... 17
Choosing a Reference for the AD5062 .................................... 17
Bipolar Operation Using the AD5062 ..................................... 17
Using AD5062 with a Galvanically Isolated Interface Chip . 18
Power Supply Bypassing and Grounding ................................ 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
5/09—Rev. 0 to Rev. A
Changes to Figure 43 ...................................................................... 17
7/05—Revision 0: Initial Version
Rev. A | Page 2 of 20
AD5062
SPECIFICATIONS
V
DD
= 5.5 V, V
REF
= 4.096 V, R
L
= Unloaded, C
L
= 22 pF to GND; T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE
Resolution
Relative Accuracy (INL)
2
Total Unadjusted Error (TUE)
Differential Nonlinearity (DNL)
Min
16
±0.5
±0.5
±500
±500
±0.5
±0.5
Gain Error
Gain Error Temperature Coefficient
Offset Error
Offset Error Temperature Coefficient
Full-Scale Error
±0.01
±0.01
1
±0.025
±0.025
0.5
±500
±500
OUTPUT CHARACTERISTICS
3
Output Voltage Range
Output Voltage Settling Time
Output Noise Spectral Density
Output Voltage Noise
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DC Output Impedance (Normal)
DC Output Impedance (Power-Down)
(Output Connected to 1 kΩ Network)
(Output Connected to 100 kΩ Network)
REFERENCE INPUT/ OUTPUT
V
REF
Input Range
2
Input Current (Power-Down)
Input Current (Normal)
DC Input Impedance
LOGIC INPUTS
Input Current
4
V
IL
, Input Low Voltage
V
IH
, Input High Voltage
Pin Capacitance
2.0
1.8
4
±1
±2
±800
±800
±1
±1
±0.02
±0.02
±0. 05
±0. 05
±800
±800
% of FSR
ppm of FSR/°C
mV
μV/°C
μV
A,B Grade
1
Typ
Max
Unit
Bits
LSB
μV
LSB
Test Conditions/Comments
−40°C to +85°C, B grade
−40°C to +85°C, A grade
−40°C to +85°C, B grade
−40°C to +85°C, A grade
Guaranteed monotonic
−40°C to +85°C, B grade
Guaranteed monotonic
−40°C to +85°C, A grade
T
A
= −40°C to +85°C B grade
T
A
= −40°C to +85°C A grade
T
A
= −40°C to + 85°C, B grade
T
A
= −40°C to + 85°C, A grade
All 1s loaded to DAC register, B grade
T
A
= −40°C to +85°C
All 1s loaded to DAC register, A grade
T
A
= −40°C to +85°C
Unipolar operation
¼ scale to ¾ scale code transition to
±1LSB.
DAC code = midscale, 1 kHz
DAC code = midscale, 0.1 to 10 Hz
bandwidth
1 LSB change around major carry
Output impedance tolerance ±20%
Output impedance tolerance ±20%
Output impedance tolerance ±20%
0
4
24
6
2
0.1
8
1
100
2
±0.1
V
REF
V
μs
nV/√Hz
μV p-p
nV-s
nV-s
kΩ
kΩ
kΩ
V
DD
− 50
±0. 5
1
±1
±2
0.8
0.8
mV
μA
μA
MΩ
μA
V
V
pF
Zero-scale loaded
Bipolar/unipolar operation
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 2.7 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
Rev. A | Page 3 of 20
AD5062
Parameter
POWER REQUIREMENTS
V
DD
I
DD
(Normal Mode)
V
DD
= 2.7 V to 5.5 V
I
DD
(All Power-Down Modes)
V
DD
= 2.5 V to 5.5 V
Power Supply Rejection Ratio (PSRR)
1
2
Min
2.7
A,B Grade
1
Typ
Max
5.5
0.65
0.7
Unit
V
mA
Test Conditions/Comments
All digital inputs at 0 V or V
DD
DAC active and excluding load current
V
IN
= V
DD
and V
IL
= GND, V
DD
= 5.5 V,
V
REF
= 4.096 V, code = midscale
V
IH
= V
DD
and V
IL
= GND V
DD
= 5.5 V,
V
REF
= 4.096 V, code = midscale
∆V
DD
± 10%, V
DD
= 5 V, unloaded
1
0.5
μA
LSB
Temperature range for the B grade: −40°C to +85°C, typical at 25°C; temperature range for the Y grade: −40°C to +125°C.
Refer to Figure 27, Figure 28, Figure 29, Figure 30, and Figure 31 for device performance under lower supply and reference voltage conditions.
3
Guaranteed by design and characterization, not production tested.
4
Total current flowing into all pins.
Rev. A | Page 4 of 20
AD5062
TIMING CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
t
1 2
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
1
2
Limit
1
33
5
3
10
3
2
0
12
9
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK fall ignore
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
Maximum SCLK frequency is 30 MHz.
t
4
SCLK
SYNC
t
2
t
3
t
1
t
7
t
9
t
8
t
6
04766-002
t
5
DIN
D23
D22
D2
D1
D0
D23
D22
Figure 2. Timing Diagram
Rev. A | Page 5 of 20
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