DS2172TN+T&R; datasheet, PDF - EEWORLD Datasheet

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DS2172TN+T&R;: DescriptionIC BIT ERROR RATE TESTER 32TQFP; Categorysemiconductor Analog mixed-signal IC; File Size173KB，22 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html; Environmental Compliance

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DS2172TN+T&R; Overview

IC BIT ERROR RATE TESTER 32TQFP

DS2172TN+T&R; Parametric

Parameter Name	Attribute value
Function	Bit Error Rate Tester (BERT)
interface	-
Number of circuits	1
Voltage - Power	4.5 V ~ 5.5 V
Current - Power	10mA
Operating temperature	-40°C ~ 85°C
Installation type	surface mount
Package/casing	32-TQFP
Supplier device packaging	32-TQFP（7x7）
include	-

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DS2172

Bit Error Rate Tester (BERT)

www.dalsemi.com

FEATURES

Generates/Detects digital bit patterns for

analyzing, evaluating and troubleshooting

digital communications systems

Operates at speeds from DC to 52 MHz

Programmable polynomial length and

feedback taps for generation of any other

pseudorandom pattern up to 32 bits in length

including: 2

-1, 2

-1,

and 2

-1

Programmable user-defined pattern and

length for generation of any repetitive pattern

up to 32 bits in length

Large 32-bit error count and bit count

registers

Software programmable bit error insertion

Fully independent transmit and receive

sections

8-bit parallel control port

Detects test patterns with bit error rates up to

-2

PIN ASSIGNMENT

TDATA

TDIS

TCLK

VSS

VDD

RCLK

RDIS

RDATA

32 31 30 29 28 27 26 25

AD0

AD1

TEST

VSS

AD2

AD3

AD4

DS2172

32-PIN TQFP

RLOS

VSS

VDD

INT

WR(R/W)

ALE(AS)

9 10 11 12 13 14 15 16

ORDERING INFORMATION

DS2172T (0

C to 70

DS2172TN (-40

C to + 85

DESCRIPTION

The DS2172 Bit Error Rate Tester (BERT) is a software programmable test pattern generator, receiver,

and analyzer capable of meeting the most stringent error performance requirements of digital

transmission facilities. Two categories of test pattern generation (Pseudo-random and Repetitive)

conform to CCITT/ITU O.151, O.152, O.153, and O.161 standards. The DS2172 operates at clock rates

ranging from DC to 52 MHz. This wide range of operating frequency allows the DS2172 to be used in

existing and future test equipment, transmission facilities, switching equipment, multiplexers, DACs,

Routers, Bridges, CSUs, DSUs, and CPE equipment.

The DS2172 user-programmable pattern registers provide the unique ability to generate loopback patterns

required for T1, Fractional-T1, Smart Jack, and other test procedures. Hence the DS2172 can initiate the

loopback, run the test, check for errors, and finally deactivate the loopback.

The DS2172 consists of four functional blocks: the pattern generator, pattern detector, error counter, and

control interface. The DS2172 can be programmed to generate any pseudorandom pattern with length up

to 2

-1 bits (see Table 5, Note 9) or any user programmable bit pattern from 1 to 32 bits in length. Logic

inputs can be used to configure the DS2172 for applications requiring gap clocking such as Fractional-T1,

Switched-56, DDS, normal framing requirements, and per-channel test procedures. In addition, the

DS2172 can insert single or 10

-1

to 10

-7

bit errors to verify equipment operation and connectivity.

1 of 23

AD5

AD6

AD7

VSS

VDD

BTS

RD(DS)

101000

DS2172

1.0 GENERAL OPERATION

1.1 PATTERN GENERATION

The DS2172 is programmed to generate a particular test pattern by programming the following registers:

Pattern Set Registers (PSR)

Pattern Length Register (PLR)

Polynomial Tap Register (PTR)

Pattern Control Register (PCR)

Error Insertion Register (EIR)

Please see Tables 4 and 5 for examples of how to program these registers in order to generate some

standard test patterns. Once these registers are programmed, the user will then toggle the TL (Transmit

Load) bit or pin to load the pattern into the onboard pattern generation circuitry and the pattern will begin

appearing at the TDATA pin.

1.2 PATTERN SYNCHRONIZATION

The DS2172 expects to receive the same pattern that it transmitted. The synchronizer examines the data at

RDATA and looks for characteristics of the transmitted pattern. The user can control the onboard

synchronizer with the Sync Enable and Resync bits in the Pattern Control Register.

In pseudorandom mode, the received pattern is tested to see if it fits the polynomial generator as defined

in the transmit side. For pseudorandom patterns, only the original pattern and an all ones pattern or an

all-0s pattern will satisfy this test. Synchronization in pseudorandom pattern mode should be qualified by

using the RA1 and RA0 indicators in the Status Register. Synchronization is declared after 34 + n bits are

received without error, where n is the exponent in the polynomial from table 4. Once in synchronization

(SR0. = 1) any deviation from this pattern will be counted by the Bit Error Count Register.

In repetitive pattern mode a received pattern of the same length as being transmitted will satisfy this test.

Synchronization in repetitive pattern mode should be qualified by using the RA1 and RA0 indicators in

the Status Register and examining the Pattern Receive Register (PRR0--3). See section 10 for an

explanation of the Pattern Receive Register. Once in synchronization (SR.0 = 1) any deviation from this

pattern will be counted by the Bit Error Count Register.

1.3 BER CALCULATION

Users can calculate the actual Bit Error Rate (BER) of the digital communications channel by reading the

bit error count out of the Bit Error Count Register (BECR) and reading the bit count out of the Bit Count

the integration period of the measurement. The LC (Load Count) bit or pin is used to set the integration

period.

1.4 GENERATING ERRORS

Via the Error Insertion Register (EIR), the user can intentionally inject a particular error rate into the

transmitted data stream. Injecting errors allows users to stress communication links and to check the

functionality of error monitoring equipment along the path.

1.5 POWER-UP SEQUENCE

On power-up, the registers in the DS2172 will be in a random state. The user must program all the

internal registers to a known state before proper operation can be insured.

2 of 22

DS2172TN+T&R; Related Products

	DS2172TN+T&R;	DS2172TN/T&R	DS2172T/T&R;	DS2172T+T&R;
Description	IC BIT ERROR RATE TESTER 32TQFP	Communication ICs - Various	IC TESTER BIT ERROR RATE 32-TQFP	IC TESTER BIT ERROR RATE 32-TQFP
Function	Bit Error Rate Tester (BERT)	-	Bit Error Rate Tester (BERT)	Bit Error Rate Tester (BERT)
Number of circuits	1	-	1	1
Voltage - Power	4.5 V ~ 5.5 V	-	4.5 V ~ 5.5 V	4.5 V ~ 5.5 V
Current - Power	10mA	-	10mA	10mA
Operating temperature	-40°C ~ 85°C	-	0°C ~ 70°C	0°C ~ 70°C
Installation type	surface mount	-	surface mount	surface mount
Package/casing	32-TQFP	-	32-TQFP	32-TQFP
Supplier device packaging	32-TQFP（7x7）	-	32-TQFP（7x7）	32-TQFP（7x7）

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