SI8233BB-C-IS1 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Analog mixed-signal IC> Drivers and interfaces> SI8233BB-C-IS1

SI8233BB-C-IS1: DescriptionDGTL ISO 2.5KV GATE DRVR 16SOIC; CategoryAnalog mixed-signal IC Drivers and interfaces; File Size619KB，56 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

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DGTL ISO 2.5KV GATE DRVR 16SOIC

SI8233BB-C-IS1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Parts packaging code	SOIC
package instruction	SOP, SOP16,.25
Contacts	16
Reach Compliance Code	unknown
ECCN code	EAR99
Built-in protection	UNDER VOLTAGE
Interface integrated circuit type	HB BASED PERIPHERAL DRIVER WITH PWM
JESD-30 code	R-PDSO-G16
length	9.9 mm
Number of functions	1
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output current flow direction	SOURCE AND SINK
Nominal output peak current	4 A
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3/5 V
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
Supply voltage 1-max	24 V
Mains voltage 1-minute	6.5 V
Supply voltage1-Nom	12 V
surface mount	YES
Temperature level	AUTOMOTIVE
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Disconnect time	60 µs
connection time	60 µs
width	3.9 mm

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Si823x

0.5

AND

4 . 0 A

I S O

D R I V E R S

(2.5

AND

RMS

)

Features



Two completely isolated drivers



60 ns propagation delay (max)

in one package



Independent HS and LS inputs or



Up to 5 kV

RMS

input-to-output

PWM input versions

isolation



Transient immunity >45 kV/µs



Up to 1500 V

peak driver-to-



Overlap protection and

driver differential voltage

programmable dead time

HS/LS and dual driver versions



AEC-Q100 qualification

Up to 8 MHz switching frequency



Wide operating range

0.5 A peak output (Si8230/1/2/7)



–40 to +125 °C



RoHS-compliant packages

4.0 A peak output

(Si8233/4/5/6/8)



SOIC-16 wide body

High electromagnetic immunity



SOIC-16



LGA-14

narrow body

Applications



Power delivery systems



Motor control systems



Isolated dc-dc power supplies



Lighting control systems



Plasma displays



Solar and industrial inverters

Safety Approval



UL 1577 recognized





VDE certification conformity



IEC

to 5000 Vrms for 1 minute

CSA component notice 5A

approval



IEC

60747-5-5 (VDE 0884 Part 5)



EN 60950-1 (reinforced

insulation)



60950-1, 61010-1, 60601-1

(reinforced insulation)

CQC certification approval



GB4943.1

Description

The Si823x isolated driver family combines two independent, isolated

drivers into a single package. The Si8230/1/3/4 are high-side/low-side

drivers, and the Si8232/5/6/7/8 are dual drivers. Versions with peak

output currents of 0.5 A (Si8230/1/2/7) and 4.0 A (Si8233/4/5/6/8) are

available. All drivers operate with a maximum supply voltage of 24 V.

The Si823x drivers utilize Silicon Labs' proprietary silicon isolation

technology, which provides up to 5 kV

RMS

withstand voltage per UL1577

and fast 60 ns propagation times. Driver outputs can be grounded to the

same or separate grounds or connected to a positive or negative voltage.

The TTL level compatible inputs with >400 mV hysteresis are available in

individual control input (Si8230/2/3/5/6/7/8) or PWM input (Si8231/4)

configurations. High integration, low propagation delay, small installed

size, flexibility, and cost-effectiveness make the Si823x family ideal for a

wide range of isolated MOSFET/IGBT gate drive applications.

Ordering Information:

See page 39.

Rev. 1.5 3/14

Si823x

Si823x

ABLE

Section

ONTENTS

Page

1. Top-Level Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

2.1. Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1. Typical Operating Characteristics (0.5 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2. Typical Operating Characteristics (4.0 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.3. Family Overview and Logic Operation During Startup . . . . . . . . . . . . . . . . . . . . . . . 21

3.4. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.5. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.6. Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.7. Undervoltage Lockout Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.8. Programmable Dead Time and Overlap Protection . . . . . . . . . . . . . . . . . . . . . . . . . 28

4. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.1. High-Side/Low-Side Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.2. Dual Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.3. Dual Driver with Thermally Enhanced Package (Si8236) . . . . . . . . . . . . . . . . . . . . .31

5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8. Land Pattern: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

11. Package Outline: 14 LD LGA (5 x 5 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

12. Land Pattern: 14 LD LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

13. Package Outline: 14 LD LGA with Thermal Pad (5 x 5 mm) . . . . . . . . . . . . . . . . . . . . .50

14. Land Pattern: 14 LD LGA with Thermal Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

15. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

15.1. Si823x Top Marking (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

15.2. Top Marking Explanation (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . 52

15.3. Si823x Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . 53

15.4. Top Marking Explanation (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . 53

15.5. Si823x Top Marking (14 LD LGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

15.6. Top Marking Explanation (14 LD LGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Rev. 1.5

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