ATMEGA88-20MUR datasheet, PDF - EEWORLD Datasheet

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ATMEGA88-20MUR: DescriptionIC MCU 8BIT 8KB FLASH 32VQFN; CategoryThe embedded processor and controller Microcontrollers and processors; File Size206KB，25 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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ATMEGA88-20MUR Overview

IC MCU 8BIT 8KB FLASH 32VQFN

ATMEGA88-20MUR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
package instruction	HVQCCN, LCC32,.2SQ,20
Reach Compliance Code	compliant
Factory Lead Time	7 weeks
Has ADC	YES
Address bus width
bit size	8
boundary scan	NO
CPU series	AVR RISC
maximum clock frequency	20 MHz
DAC channel	NO
DMA channel	NO
External data bus width
Format	FIXED-POINT
Integrated cache	NO
JESD-30 code	S-PQCC-N32
JESD-609 code	e3
length	5 mm
low power mode	YES
Humidity sensitivity level	1
Number of external interrupt devices	2
Number of I/O lines	23
Number of serial I/Os	1
Number of terminals	32
Number of timers	3
On-chip data RAM width	8
On-chip program ROM width	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	HVQCCN
Encapsulate equivalent code	LCC32,.2SQ,20
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	3/5 V
Certification status	Not Qualified
RAM (bytes)	1024
RAM (number of words)	1024
rom(word)	4096
ROM programmability	FLASH
Maximum seat height	1 mm
speed	20 MHz
Maximum slew rate	12 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	2.7 V
Nominal supply voltage	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	5 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC
Base Number Matches	1

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Features

•

High Performance, Low Power AVR

8-Bit Microcontroller

•

Advanced RISC Architecture

– 131 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Throughput at 20 MHz

– On-chip 2-cycle Multiplier

Non-volatile Program and Data Memories

– 4/8/16K Bytes of In-System Self-Programmable Flash (ATmega48/88/168)

Endurance: 10,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– 256/512/512 Bytes EEPROM (ATmega48/88/168)

Endurance: 100,000 Write/Erase Cycles

– 512/1K/1K Byte Internal SRAM (ATmega48/88/168)

– Programming Lock for Software Security

Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Six PWM Channels

– 8-channel 10-bit ADC in TQFP and QFN/MLF package

– 6-channel 10-bit ADC in PDIP Package

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Byte-oriented 2-wire Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change

Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated Oscillator

– External and Internal Interrupt Sources

– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and

Standby

I/O and Packages

– 23 Programmable I/O Lines

– 28-pin PDIP, 32-lead TQFP and 32-pad QFN/MLF

Operating Voltage:

– 1.8 - 5.5V for ATmega48V/88V/168V

– 2.7 - 5.5V for ATmega48/88/168

Temperature Range:

– -40

C to 85

Speed Grade:

– ATmega48V/88V/168V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V

– ATmega48/88/168: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V

•

8-bit

Microcontroller

with 8K Bytes

In-System

Programmable

Flash

ATmega48/V

ATmega88/V

ATmega168/V

Preliminary

Summary

•

Rev. 2545ES–AVR–02/05

Note: This is a summary document. A complete document

is available on our Web site at www.atmel.com.

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATmega48/88/168 provides the following features: 4K/8K/16K bytes of In-System Program-

mable Flash with Read-While-Write capabilities, 256/512/512 bytes EEPROM, 512/1K/1K bytes

SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible

Timer/Counters with compare modes, internal and external interrupts, a serial programmable

USART, a byte-oriented 2-wire Serial Interface, an SPI serial port, a 6-channel 10-bit ADC (8

channels in TQFP and QFN/MLF packages), a programmable Watchdog Timer with internal

Oscillator, and five software selectable power saving modes. The Idle mode stops the CPU

while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port, and inter-

rupt system to continue functioning. The Power-down mode saves the register contents but

freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset.

In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a

timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the

CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise dur-

ing ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest

of the device is sleeping. This allows very fast start-up combined with low power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The

On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI

serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro-

gram running on the AVR core. The Boot program can use any interface to download the

application program in the Application Flash memory. Software in the Boot Flash section will

continue to run while the Application Flash section is updated, providing true Read-While-Write

operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a

monolithic chip, the Atmel ATmega48/88/168 is a powerful microcontroller that provides a highly

flexible and cost effective solution to many embedded control applications.

The ATmega48/88/168 AVR is supported with a full suite of program and system development

tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emu-

lators, and Evaluation kits.

2.2

Comparison Between ATmega48, ATmega88, and ATmega168

The ATmega48, ATmega88 and ATmega168 differ only in memory sizes, boot loader support,

and interrupt vector sizes.

Table 2-1

summarizes the different memory and interrupt vector sizes

for the three devices.

Table 2-1.

Device

ATmega48

ATmega88

ATmega168

Memory Size Summary

Flash

4K Bytes

8K Bytes

16K Bytes

EEPROM

256 Bytes

512 Bytes

RAM

512 Bytes

1K Bytes

Interrupt Vector Size

1 instruction word/vector

2 instruction words/vector

ATmega88 and ATmega168 support a real Read-While-Write Self-Programming mechanism.

There is a separate Boot Loader Section, and the SPM instruction can only execute from there.

ATmega48/88/168

2545ES–AVR–02/05

ATmega48/88/168

In ATmega48, there is no Read-While-Write support and no separate Boot Loader Section. The

SPM instruction can execute from the entire Flash.

2.3

2.3.1

Pin Descriptions

VCC

Digital supply voltage.

2.3.2

GND

Ground.

2.3.3

Port B (PB7..0) XTAL1/XTAL2/TOSC1/TOSC2

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscil-

lator amplifier and input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PB7 can be used as output from the inverting

Oscillator amplifier.

If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1

input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.

The various special features of Port B are elaborated in

”Alternate Functions of Port B” on page

and

”System Clock and Clock Options” on page 25.

2.3.4

Port C (PC5..0)

Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

PC5..0 output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

2.3.5

PC6/RESET

If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical char-

acteristics of PC6 differ from those of the other pins of Port C.

If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin

for longer than the minimum pulse length will generate a Reset, even if the clock is not running.

The minimum pulse length is given in

Table 8-1 on page 44.

Shorter pulses are not guaranteed

to generate a Reset.

The various special features of Port C are elaborated in

”Alternate Functions of Port C” on page

75.

2.3.6

Port D (PD7..0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

2545ES–AVR–02/05

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