AX-SFAZ, AX-SFAZ-API
Ultra-Low Power,
AT Command / API Controlled,
Sigfox
)
Compliant
Transceiver IC for Up-Link
and Down-Link
OVERVIEW
Circuit Description
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AX−SFAZ and AX−SFAZ−API are ultra−low power
single chip solutions for a node on the Sigfox network with
both up− and down−link functionality. The AX−SFAZ chip
is delivered fully ready for operation and contains all the
necessary firmware to transmit and receive data from the
Sigfox network in Australia/New Zealand (SIGFOX RCZ4
region). It connects to the customer product using a logic
level RS232 UART. AT commands are used to send frames
and configure radio parameters.
The AX−SFAZ−API variant is intended for customers
wishing to write their own application software based on the
AX−SF−LIB−1−GEVK library.
Features
•
8 GPIO pins
♦
♦
♦
♦
♦
2 GPIO pins with selectable voltage measure
functionality, differential (1 V or 10 V range) or
single ended (1 V range) with 10 bit resolution
2 GPIO pins with selectable sigma delta DAC
output functionality
2 GPIO pins with selectable output clock
3 GPIO pins selectable as SPI master interface
RX/TX switching Control
Functionality and Ecosystem
•
Sigfox up−link and down−link functionality controlled
by AT commands or API
•
The AX−SFAZ and AX−SF−API ICs are part of a
whole development and product ecosystem available
from ON Semiconductor for any Sigfox requirement.
Other parts of the ecosystem include
♦
Ready to go development kit
DVK−SFAZ−[API]−1−GEVK including a 2 year
Sigfox subscription
♦
Sigfox Ready
®
certified reference design for the
AX−SFAZ and AX−SFAZ−API ICs
General Features
•
QFN40 5 mm x 7 mm package
•
Supply range 2.7 V
*
−
3.6 V
•
−40°C
to 85°C
•
Temperature sensor
•
Supply voltage measurements
*Includes the RF frontend module, circuit as in Figure 5.
The AX−SFAZ chip alone is operational from 1.8 V to 3.6 V,
a supply voltage below 2.0 V is considered an extreme condition.
Power Consumption
•
Ultra−low Power Consumption:
♦
Charge required to send a Sigfox OOB packet at
24 dBm output power: 0.28 C
♦
Deepsleep mode current: 100 nA
♦
Sleep mode current: 1.3
mA
♦
Standby mode current: 0.5 mA
♦
Continuous radio RX−mode at 922.3 MHz :
34 mA
♦
Continuous radio TX−mode at 920.8 MHz
230 mA @ 24 dBm
High Performance Narrow−band Sigfox RF Transceiver
•
Receiver
♦
Carrier frequency 922.3 MHz
♦
Data−rate 600 bps FSK
♦
Sensitivity
−128
dBm @ 600 bps, 922.3 MHz, GFSK
♦
0 dBm maximum input power
•
Transmitter
♦
Carrier frequency 920.8 MHz
♦
Data−rate 600 bps PSK
♦
High efficiency, high linearity integrated power
amplifier
♦
Maximum output power 24 dBm
Applications
Sigfox networks up−link and down−link.
©
Semiconductor Components Industries, LLC, 2017
April, 2017
−
Rev. 1
1
Publication Order Number:
AX−SFAZ/D
AX−SFAZ, AX−SFAZ−API
BLOCK DIAGRAM
AX−SFAZ / AX−SFAZ−API
CLKP
CLKN
TCXO
interface
RF synthesis
CAL
FILT
ANTP1
PA
Transmit
Communication
controller
ANTP
ANTN
LNA
Receive
UARTRX
UARTTX
UART
DAC
GPIO[9:4,1:0]
GPIO
ADC
CPU
RADIO_LED
CPU_LED
TX_LED
RX_LED
TX_EN
RX_EN
dedicated
status
outputs
power mode control
RAM
Program
memory
(FLASH)
Sigfox identity (ID, PAC)
Sigfox compliant
application
VDD_ANA
VDD_IO
GND
VTCXO
Figure 1. Functional Block Diagram of the AX−SFAZ / AX−SFAZ−API
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2
RESET_N
AX−SFAZ, AX−SFAZ−API
Table 1. PIN FUNCTION DESCRIPTIONS
Symbol
VDD_ANA
GND
ANTP
ANTN
ANTP1
GND
VDD_ANA
GND
FILT
L2
L1
NC
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
CPU_LED
RADIO_LED
VTCXO
GPIO9
UARTTX
UARTRX
RX_LED
TX_LED
NC
RESET_N
GND
VDD_IO
GPIO0
GPIO1
TX_EN
NC
NC
RX_EN
VDD_IO
CAL
NC
CLKN
Pin(s)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Type
P
P
A
A
N
P
P
P
A
A
A
N
I/O/PU
I/O/PU
I/O/PU
I/O/PU
I/O/PU
O
O
O
I/O/PU
O
I/PU
O
O
PD
I/PU
P
P
I/O/A/PU
I/O/A/PU
O
N
N
O
P
A
N
A
Description
Analog power output, decouple to neighboring GND
Ground, decouple to neighboring VDD_ANA
Differential receive input
Differential receive input
Single ended transmit output
Ground, decouple to neighboring VDD_ANA
Analog power output, decouple to neighboring GND
Ground
Synthesizer filter
Must be connected to pin L1
Must be connected to pin L2
Do not connect
General purpose IO
General purpose IO, selectable SPI functionality (MISO)
General purpose IO, selectable SPI functionality (MOSI)
General purpose IO, selectable SPI functionality (SCK)
General purpose IO, selectable
SD
DAC functionality, selectable dock
functionality
CPU activity indicator
Radio activity indicator
TCXO power
General purpose IO, wakeup from deep sleep
UART transmit
UART receive
Receive activity indicator
Transmit activity indicator
Do not connect
Optional reset pin. Internal pull−up resistor is permanently enabled,
nevertheless it is recommended to connect this pin to VDD_IO if it is not used.
Ground
Unregulated power supply
General purpose IO, selectable ADC functionality, selectable
SD
DAC
functionality, selectable clock functionality
General purpose IO, selectable ADC functionality
Transmitter Enable (to frontend)
Do not connect
Do not connect
Receiver Enable (to frontend)
Unregulated power supply
Connect to FILT as shown in the application diagram
Do not connect
TCXO interface
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AX−SFAZ, AX−SFAZ−API
Table 1. PIN FUNCTION DESCRIPTIONS
Symbol
CLKP
GND
Pin(s)
40
Center pad
Type
A
P
TCXO interface
Ground on center pad of QFN, must be connected
Description
A = analog input
I = digital input signal
O = digital output signal
PU = pull−up
I/O = digital input/output signal
N = not to be connected
P = power or ground
PD = pull−down
All digital inputs are Schmitt trigger inputs, digital input
and output levels are LVCMOS/LVTTL compatible. Pins
GPIO[3:0] must not be driven above VDD_IO, all other
digital inputs are 5 V tolerant. All GPIO pins and UARTRX
start up as input with pull−up. For explanations on how to
use the GPIO pins, see chapter “AT Commands”.
Table 2.
Pin
GPIO0
GPIO1
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
Possible GPIO Modes
0, 1, Z, U, A, T
0, 1, Z, U, A
0, 1, Z, U, T
0, 1, Z, U
0, 1, Z, U
0, 1, Z, U
0, 1, Z, U
0, 1, Z, U
0 = pin drives
1 = not to be connected
Z = pin is high impedance input
U = pin is input with pull−up
A = pin is analog input
T = pin is driven by clock or DAC
Pinout Drawing
VDD_IO
RX_EN
TX_EN
GPIO1
VDD_IO
29
40
39
38
37
36
35
NC
34
33
32
31
VDD_ANA
GND
ANTP
ANTN
ANTP1
GND
VDD_ANA
GND
GPIO0
30
CLKN
CLKP
CAL
NC
NC
1
28
GND
RESET_N
NC
TXLED
RXLED
UARTRX
UARTTX
GPIO9
2
27
3
26
4
AX−SFAZ / AX−SFAZ−API
QFN40
25
5
24
6
23
7
22
8
21
9
10
11
12
13
14
15
16
17
18
19
20
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
RADIO_LED
Figure 2. Pinout Drawing (Top View)
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4
CPU_LED
VTCXO
FILT
NC
L2
L1
AX−SFAZ, AX−SFAZ−API
SPECIFICATIONS
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol
VDD_IO
IDD
P
tot
P
i
I
I1
I
I2
I
O
V
ia
V
es
T
amb
T
stg
T
j
Supply voltage
Supply current
Total power consumption
Absolute maximum input power at receiver input
DC current into any pin except ANTP, ANTN, ANTP1
DC current into pins ANTP, ANTN, ANTP1
Output Current
Input voltage ANTP, ANTN, ANTP1 pins
Input voltage digital pins
Electrostatic handling
Operating temperature
Storage temperature
Junction Temperature
HBM
−0.5
−0.5
−2000
−40
−65
ANTP and ANTN
pins in RX mode
−10
−100
Description
Condition
Min
−0.5
Max
5.5
200
800
10
10
100
40
5.5
5.5
2000
85
150
150
Units
V
mA
mW
dBm
mA
mA
mA
V
V
V
°C
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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