ZL50120GAG2 datasheet, PDF - EEWORLD Datasheet

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ZL50120GAG2: DescriptionSPECIALTY TELECOM CIRCUIT, PBGA324; CategoryWireless rf/communication Telecom circuit; File Size1MB，95 Pages; ManufacturerZarlink Semiconductor (Microsemi); Websitehttp://www.zarlink.com/; Environmental Compliance

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ZL50120GAG2 Overview

SPECIALTY TELECOM CIRCUIT, PBGA324

ZL50120GAG2 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Zarlink Semiconductor (Microsemi)
package instruction	BGA, BGA324,22X22,40
Reach Compliance Code	unknow
JESD-30 code	S-PBGA-B324
JESD-609 code	e1
length	23 mm
Number of functions	1
Number of terminals	324
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA324,22X22,40
Package shape	SQUARE
Package form	GRID ARRAY
power supply	1.8,3.3 V
Certification status	Not Qualified
Maximum seat height	2.16 mm
Nominal supply voltage	1.8 V
surface mount	YES
Telecom integrated circuit types	TELECOM CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	23 mm

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ZL50115/16/17/18/19/20

32, 64 and 128 Channel CESoP

Processors

Data Sheet

Features

General

•

Circuit Emulation Services over Packet (CESoP)

transport for MPLS, IP and Ethernet networks

On chip timing & synchronization recovery across

a packet network

On chip dual reference Stratum 3 DPLL

Grooming capability for Nx64 Kbps trunking

Fully compatible with Zarlink's ZL50110, ZL50111

and ZL50114 CESoP processors

Ordering Information

ZL50115GAG

324 Ball PBGA

trays, bake

ZL50116GAG

324 Ball PBGA

trays, bake

ZL50117GAG

324 Ball PBGA

trays, bake

ZL50118GAG

324 Ball PBGA

trays, bake

ZL50119GAG

324 Ball PBGA

trays, bake

ZL50120GAG

324 Ball PBGA

trays, bake

ZL50115GAG2 324 Ball PBGA** trays, bake

ZL50116GAG2 324 Ball PBGA** trays, bake

ZL50117GAG2 324 Ball PBGA** trays, bake

ZL50118GAG2 324 Ball PBGA** trays, bake

ZL50119GAG2 324 Ball PBGA** trays, bake

ZL50120GAG2 324 Ball PBGA** trays, bake

**Pb Free Tin/Silver/Copper

dry

pack

February 2006

Circuit Emulation Services

•

Complies with ITU-T recommendation Y.1413

Complies with IETF PWE3 draft standards

CESoPSN and SAToP

Complies with CESoP Implementation

Agreements from MEF 8 and MFA 8.0.0

Structured, synchronous CESoP with clock

recovery

Unstructured, asynchronous CESoP with integral

per-stream clock recovery

•

-40°C to +85°C

Up to 128 bi-directional 64 Kbps channels

Direct connection to LIUs, framers, backplanes

Customer Side Packet Interfaces

• 100 Mbps MII Fast Ethernet (ZL50118/19/20 only)

(may also be used as a second provider side packet

interface)

Provider Side Packet Interfaces

•

100 Mbps MII Fast Ethernet or 1000 Mbps

GMII/TBI Gigabit Ethernet

Customer Side TDM Interfaces

•

Up to 4 T1/E1, 1 J2, 1 T3/E3, or 1 STS-1 ports

H.110, H-MVIP, ST-BUS backplane

4 T1/E1, 1 J2/T3/E3 or 1 STS-1 ports

H.110, H-MVIP, ST-BUS backplanes

TDM

Interface

(LIU, Framer, Backplane)

Multi-Protocol

Packet

Processing

Engine

PW, RTP, UDP,

IPv4, IPv6, MPLS,

ECID, VLAN, User

Defined, Others

Dual

Packet

Interface

MAC

(MII, GMII, TBI)

Per Port DCO for

Clock Recovery

100 Mbps MII

Fast Ethernet

On Chip Packet Memory

(Jitter Buffer Compensation for 128 ms of Packet Delay Variation)

Dual Reference

Stratum 3 DPLL

Host Processor

Interface

32-bit Motorola compatible

DMA for signaling packets

Backplane

Clocks

JTAG

Figure 1 - ZL50115/16/17/18/19/20 High Level Overview

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

100 Mbps MII Fast Ethernet

1000 Mbps GMII/TBI Gigabit Ethernet

ZL50115/16/17/18/19/20

2.0

Description

Data Sheet

The ZL5011x family (ZL50115, ZL50116, ZL50117, ZL50118, ZL50119, ZL50120) of CESoP processors are highly

functional TDM to Packet bridging devices. The ZL5011x provides both structured and unstructured circuit

emulation services (CESoP) for T1 and E1 streams across a packet network based on MPLS, IP or Ethernet. The

ZL50117/20 also supports unstructured J2, T3, E3 and STS-1.

The circuit emulation features in the ZL5011x family comply with the ITU Recommendation Y.1413, as well as the

Implementation Agreements for CESoP from the Metro Ethernet Forum (MEF 8) and the MPLS and Frame Relay

Alliance (MFA 8.0.0). The ZL5011x also complies with the standards currently being developed within the IETF's

PWE3 working group, listed below.

•

Structure-Agnostic TDM over Packet (SAToP) - draft-ietf-pwe3-satop

Structure-aware TDM Circuit Emulation Service over Packet Switched Network (CESoPSN) -

draft-ietf-pwe3-cesopsn

The ZL50118/19/20 provides a customer side 100 Mbps MII port to aggregate data traffic with voice traffic to the

provider side 1000 Mbps GMII/TBI port, thereby eliminating the need for an external Ethernet switch.

The ZL5011x incorporates a range of powerful clock recovery mechanisms for each TDM stream, allowing the

frequency of the source clock to be faithfully generated at the destination, enabling greater system performance

and quality. Timing is carried using RTP or similar protocols, and both adaptive and differential clock recovery

schemes are included, allowing the customer to choose the correct scheme for the application. An externally

supplied clock may also be used to drive the TDM interface of the ZL5011x.

The ZL5011x incur very low latency for the data flow, thereby increasing QoS when carrying voice services across

the Packet Switched Network. Voice, when carried using CESoP, which typically has latencies of less than 10 ms,

does not require expensive processing such as compression and echo cancellation.

The ZL5011x are cost effective devices aimed at the low density applications such as customer premise routers,

IADs, ePON termination and Broadband DLCs. For network systems, the ZL5011x is fully compatible and

interoperable with the ZL50110/11/14 family.

The ZL5011x is capable of assembling user-defined packets of TDM traffic from the TDM interface and transmitting

them out the packet interfaces using a variety of protocols. The ZL5011x supports a range of different packet

switched networks, including Ethernet VLANs, IP (both versions 4 and 6) and MPLS. The devices also supports

four different classes of service on packet egress, allowing priority treatment of TDM-based traffic. This can be used

to help minimize latency variation in the TDM data.

Packets received from the packet interfaces are parsed to determine the egress destination, and are appropriately

queued to the TDM interface, they can also be forwarded to the host interface, or back toward the packet interface.

Packets queued to the TDM interface can be re-ordered based on sequence number, and lost packets filled in to

maintain timing integrity.

The ZL5011x includes on-chip memory sufficient for all applications, thereby reducing system costs, board area,

power, and design complexity.

A comprehensive evaluation system is available upon request from your local Zarlink representative or distributor.

This system includes the CESoP processor, various TDM interfaces and a fully featured evaluation software GUI

that will run on a Windows PC.

Zarlink Semiconductor Inc.

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