ZL30226/7/8
4/8/16 Port IMA/TC PHY Device for xDSL
Data Sheet
Features
IMA
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Up to 16 xDSL links & up to 8 IMA groups with 1
to 16 links/IMA group
1
Supports symmetrical & asymmetrical operation
CTC (common transmit) & ITC (independent
transmit) clocking modes
Pre-processing of RX ICP (IMA control protocol)
cells
IMA layer & per link statistics and alarms for
performance monitoring with MIB support
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Ordering Information
ZL30226/GA
ZL30227/GA
ZL30228/GA
384 Pin PBGA
384 Pin PBGA
384 Pin PBGA
March 2004
-40°C to +85°C
HEC (header error control) verification &
generation, error detection, filler cell filtering
(IMA) and idle/unassigned cell filtering (TC)
TC layer statistics and error counts i.e. HEC
errors with MIB support
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TC and UNI
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Supports mixed-mode operation: links not
assigned to an IMA group can be used in TC
mode
ATM framing using cell delineation
Standards Compliant
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ATM Forum - IMA 1.1 (AF-PHY-0086.001) &
backwards compatible with IMA 1.0
ITU G.804 cell mapping & ITU I.432 cell
delineation
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1. ZL30226 supports up to 4 serial links with maximum 4 groups
to be used - groups 0, 1, 2, 3.
ZL30227 supports up to 8 serial links
ZL30228 supports up to 16 serial links
RX External Static RAM
TDM Ring
RX
Utopia
Level 2
BUS
TX
Rx Utopia
FIFo
Internal IMA
Processors
(1 per group)
TDM
Ring
Control
S/P
xDSL
Utopia
I/F CTRL
Cell
Delineator
CD Circuits (1 per link)
xDSL
P/S
Tx Utopia
FIFo
Transmission
Convergence
TDM
Ring
Control
xDSL
Serial TDM Ports
(1 per link, up to 10Mb/s
per link)
TC Circuits (1 per link)
Processor I/F
TDM Ring
Figure 1 -
ZL30226/7/8 Block Diagram with Built-in IMA functions
for up to 8 IMA Groups over 4/8/16 links
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30226/7/8
General
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Supports TDM serial links up to 10 Mb/s for xDSL
Single chip ATM IMA & TC processor
Versatile TDM interface for most popular xDSL chipsets
Up to 6 ZL30226/7/8 devices can be spanned using a TDM ring supporting 32 links
Data Sheet
Provides 8 & 16-bit UTOPIA Level 1 & 2 compatible MPHY Interface (ZL30226/7/8 slaved to ATM device)
16-bit microprocessor interface for Intel or Motorola
JTAG test support
2.5 V core, 3.3 V I/O with 5 V tolerant inputs
384 pin PGBA with 1.0 mm pitch balls
ZL30226, ZL30227 and ZL30228 share the same product package and pin-out configuration
Applications
Provides cost effective solutions to implement IMA and/or TC functions over xDSL transport facilities in broadband
access networks. Typical applications are for trunking or subscriber access in:
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Integrated access devices
Access multiplexers
Next-generation DLC
Overview
The ZL30226, ZL30227 and ZL30228 form a family of similar devices, differing mainly in the maximum number of
serial links, and are collectively referred to as ZL30226/7/8. It should be noted throughout this document whenever
reference is made to the number of serial links that the ZL30228 offers a maximum of 16 serial links (links 15:0),
while the ZL30227 offers a maximum of 8 serial links (links 14, 12, 10, 8, 6, 4, 2 and 0), and the ZL30226 offers a
maximum of 4 serial links (links 12, 8, 4 and 0). Pin and register compatibility has been maintained to offer
interchangeability.
Note:
When creating IMA groups for ZL30226 the groups 0,1,2 and 3 should be used.
Description
The ZL30226/7/8 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA
version 1.1 and 1.0) or UNI specifications. In the ZL30226/7/8 architecture, up to 16 physical and independent
serial links can be terminated through the utilization of off-the-shelf xDSL chip sets. The ZL30226/7/8 can provide
up to 10 Mb/s per link data rates for TDM serial transmissions for xDSL applications.
The ZL30226/7/8 device provides ATM system designers with a flexible architecture when implementing ATM
access over existing line interfaces, allowing a migration towards ATM service technology. The ZL30226/7/8 device
is compliant with the ATM FORUM IMA specifications for controlling IMA groups of up to 16 lines in a single chip.
The ZL30226/7/8 can be configured to operate in different modes to facilitate the implementation of the IMA
function at both CPE and Central Office sites. For systems targeting ATM over DSL with IMA and TC operating
simultaneously, the ZL30226/7/8 device provides the ideal architecture and capabilities.
The device provides up to 8 internal IMA processors and allows for bandwidth scaleability through the use of the
UTOPIA MPHY, Level 1 and Level 2 specification at rates up to 52 Mhz.
The implementation of IMA as per AF-PHY-0086.001 Inverse Multiplexing for ATM (IMA) Specification Version 1.1
is divided into hardware and software functions. Hardware functions are implemented in the ZL30226/7/8 device
and software functions are implemented by the IMA Core (Zarlink or user) software. Additional hardware functions
are included to assist in the collection of statistical information to support MIB implementation.
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Zarlink Semiconductor Inc.
ZL30226/7/8
Hardware functions that are implemented in the ZL30226/7/8 device are:
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Utopia Level 1 or 2 compatible MPHY Interface
Incoming HEC verification and correction (optional)
Generation of a new HEC byte
Format outgoing cells into multi-vendor serial TDM formats
Retrieve ATM Cells from the incoming multi-vendor serial TDM format
Perform cell delineation
Cell pre-processing
Provide various counters to assist in performance monitoring
TDM expansion ring to span multiple devices
Data Sheet
Hardware functions that are implemented by the IMA processor in the ZL30226/7/8 device are:
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Transmit scheduler (one per IMA group)
Generation of the TX IMA Data Cell Rate clock
Generation and insertion of ICP cells, Filler Cells and Stuff Cells in IMA mode and Idle Cells in TC mode; the
ICP cells are programmed by the user and the Filler and Idle cells are pre-defined
Perform IMA Frame synchronization
Retrieve and process Rx ICP cells in IMA Mode
Management of RX links to be part of the internal re-sequencer when active
Extraction of RX IMA Data Cell Rate clock
Verification of delays between links
Perform re-sequencing of ATM cells using external asynchronous Static RAM
Can accommodate more than 200 msec of link differential delay depending on the amount of external
memory
Provide structured Interrupt scheme to report various events
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Zarlink Semiconductor Inc.
ZL30226/7/8
Table of Contents
Data Sheet
1.0 Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.1 Software Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.1.1 Link State Machines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.1.2 IMA Group State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.1.3 Link Addition, Removal or Restoration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.1.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.1.5 Signalling and Rate Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.1.6 Performance Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.2 Hardware Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.0 The ATM Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.1 Cell In Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2 The ATM Transmission Convergence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2.1 TX Cell RAM and TX FIFO Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.3 Parallel to Serial TDM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.4 ATM Transmit Path in IMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.4.1 IMA Frame Length (M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.4.2 Position of the ICP Cell in the IMA Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.4.3 Transmit Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.4.4 Stuff Cell Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.4.5 IMA Data Cell Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.4.6 IMA Controller (RoundRobin Scheduler) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.4.7 ICP Cell Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.4.8 IMA Frame Programmable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.4.9 Filler Cell Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.4.10 TX IMA Group Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.4.11 TX Link Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.4.12 TX Link Deletion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.5 ATM Transmit Path in TC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.0 The ATM Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.1 Cell Delineation Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2 De-Scrambling and ATM Cell Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3 ATM Receive Path in IMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.1 ICP Cell Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.2 IMA Frame Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.3 Link Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.4 RX OAM Label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.5 Out of IMA Frame (OIF) Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.6 Loss of IMA Frame (LIF) Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3.7 Filler Cell Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3.8 Stuff Cell Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3.9 Received ICP Cell Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3.10 Rate Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3.11 Cell Buffer/RAM Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3.12 Cell Sequence Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3.13 Delay Between Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3.13.1 RX Recombiner Delay Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3.13.2 RX Maximum Operational Delay Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3.13.3 Link Out of Delay Synchronization (LODS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3.13.4 Negative Delay Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3.13.5 Measured Delay Between Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.3.13.6 Incrementing/Decrementing the Recombiner Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.3.14 RX IMA Group Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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Zarlink Semiconductor Inc.
ZL30226/7/8
Table of Contents
Data Sheet
3.3.15 Link Addition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.3.16 Link Deletion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.3.17 Disabling an IMA Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.4 The ATM Receive Path in TC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.0 Description of the TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.1 Non-Framed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.1.1 Non-Framed Mode - 2.5 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.1.2 Non-Framed Mode - 5.0 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.1.3 Non-Framed Mode - 10.0 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.2 Clock format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.3 TDM Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.4 .Serial to Parallel (S/P) and Parallel to Serial (P/S) Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.5 Clocking Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.5.1 Primary and Secondary Reference Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.5.2 Verification of Clock Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.5.3 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.0 UTOPIA Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.1 ATM Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.2 ATM Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.3 UTOPIA Operation With a Single PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.4 UTOPIA Operation with Multiple PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.5 UTOPIA Operation in TC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.6 UTOPIA Operation in IMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.7 UTOPIA Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.8 Examples of UTOPIA Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.0 Support Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.1 Counter Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.1.1 UTOPIA Input I/F counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.1.2 Transmit TDM I/F Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.1.3 Receive TDM I/F Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.1.4 Access to the Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.1.5 Latching counter mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.2 Interrupt Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.2.1 IRQ Master Status and IRQ Master Enable Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.2.2 IRQ Link Status and IRQ Link Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.2.2.1 Bit 8 and 7 of IRQ Link 0 Status and IRQ Link 0 Enable Registers. . . . . . . . . . . . . . . . . . . . 65
6.2.3 IRQ Link TC Overflow Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.2.4 IRQ IMA Group Overflow Status and Enable Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.2.5 IRQ IMA Overflow Status and RX UTOPIA IMA Group FIFO Overflow Enable Registers . . . . . . . 66
6.3 Microprocessor Interface Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.1 Access to the Various Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.2 Direct Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.3 Indirect Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.4 Clearing of Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.4.1 Toggle Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.4 Cell Preprocessor Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.5 TDM Ring Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.6 SRAM decoding for ZL30226 and ZL30227 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7.0 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7.1 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7.2 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5
Zarlink Semiconductor Inc.
Analogue and Mixed Signal
京公网安备 11010802033920号
EEWORLD
